Dynamic content addressable memory cell

Details Dynamic content addressable memory cell Dynamic content addressable memory cell

2001-10-17

2002-11-19

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189070

Reexamination Certificate

active

06483733

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to dynamic content addressable memory (CAM), and more specifically to dynamic content addressable memory cells suitable for constructing high-speed, large-capacity dynamic CAM arrays.
2. Description of the Background Art
Content addressable memory (CAM) is a memory in which a group of memory elements are selected or identified by their content, rather than by their physical location. Generally, CAM includes a matrix of CAM cells arranged in rows and columns. Each CAM cell stores one bit of digital data and includes a circuit to allow comparing the stored data with externally provided search data. One or more bits of information in a row constitute a word. A content addressable memory compares a search word with a set of words stored within the CAM. During a search-and-compare operation, an indicator associated with each stored word produces a comparison result, indicating whether or not the search word matches the stored word.
There are several known approaches to CAM cells in the art. A journal paper by Kenneth J. Schultz entitled “Content-addressable Memory Cells-A Survey” published in Integration, the VLSI Journal, Vol. 23, pp. 171-188, 1997 describes several CAM cell designs and summarizes the advantages and disadvantages of each. Some of the prior art CAM cells use a static storage element while others use a dynamic storage element. Dynamic storage elements occupy a smaller area on a semiconductor substrate and are therefore preferable to obtain a larger memory capacity on a single integrated circuit chip. Another advantage of the dynamic storage cell is a potential for ternary storage where in addition to the 0 and 1 state, a third “don't care” state can be stored by having similar charges on the two storage capacitors. The original 5-transistor dynamic CAM cell was published by Mundy el al. in “Low-cost associative memory” IEEE Journal of Solid-State Circuits SC-
7
(1972) 364-369. See also U.S. Pat. No. 3,701,980 to Mundy.
FIG. 1
illustrates the dynamic CAM cell of Mundy et al. redrawn and re-labelled for consistency with an illustration of the present invention given in FIG.
2
. As shown in
FIG. 1
, the prior art first CAM cell
1
has a dynamic storage element in the form of capacitors C
1
and C
2
which are accessed at bit lines BL
1
and BL
2
via transistors T
1
and T
2
respectively. A write or a read operation is performed by turning T
1
and T
2
on using the word line WL while the match line ML
i
is held low to permit date transfer from BL
1
and BL
2
to C
1
and C
2
, and vice versa. In a search and compare operation, T
1
and T
2
are held off by a low WL signal, while BL
1
, B
2
and ML
i
are precharged high. Search data is then driven on BL
1
and BL
2
. If the data stored on C
1
is high but search data driven on BL
1
is low, current i
1
will discharge the ML
i
through T
4
and T
3
. Similarly, if the data stored on C
2
is high and the search data driven onto BL
2
is low, the ML
i
will discharged. If the search data applied to BL
1
and BL
2
match the data stored on C
1
and C
2
respectively, no current path exists from ML
i
to either BL
1
or BL
2
and the ML
i
remains at the precharged high level.
FIG. 1
also shows a second CAM cell
2
in a different word, which has a different matchline, ML
i-1
. The voltage level of ML
i-1
in a search operation is also influenced by the search data placed on BL1 and BL2 and the values stored on C3 and C4.
There are two disadvantages associated with the prior art CAM cell of FIG.
1
. First, the capacitance of bit lines BL
1
and BL
2
varies depending on the data stored in individual CAM cells connected to those bit lines. Second, the voltage on any one match line (e.g. ML
i
or ML
i−1
) obtained during a search-and-compare operation depends not only on the data stored in one word, but also data stored in other words within a given subarray of CAM cells. This occurs because the bit line drivers T
3
and T
4
have limited current capability, but may be required to discharge several match lines, depending on the data content of cells associated with BL
1
and BL
2
(e.g. data stored in the first cell
1
and the second cell
2
).
These disadvantages place a limit on the number of cells that can be connected to one particular bit line, thereby limiting the size of a subarray and making it more difficult to design a reliable circuit for detecting voltage levels on match lines.
Several variations from the original proposal by Mundy et al. exist in the literature. These include the CAM cell published by Wade ans Sodini in: “Dynamic corss-coupled bit line content addressable memory cell for high density arrays”, IEDM Digital Technology Papers (1985), 284-287. See also U.S. Pat. No. 4,831,585 to Wade and Sodini. Another improved CAM cell which uses a dynamic latch circuit, was published by Jones in: “Design, Selection and Implementation of a content-addressable memory: alternatives to the ubiquitous RAM”, IEEE Computers 22 (1989), 51-64. Yet none of these cited improvements adequately address the problem of variations in bit line capacitance and match line voltage detection.
Kadota et al. presented one static CAM design in: “An 8-Kbit content-addressable and reentrant memory”, IEEE Journal on Solid State Circuits SC-20 (1985), 951-957. See also U.S. Pat. No. 4,823,313 to Kadota. In this design, a pair of active pull-down circuits are used between the match line and a ground terminal, each consisting of two transistors in series; the gate of one transistor is connected to one of the two cells nodes and gate of the other transistor is connected to the corresponding bit line. With the storage device being of the static type, the CAM cell in the Kadota design is limited to binary storage. In order to be able to store a third “don't care”state, an additional storage device would be required.
All the prior art CAM cells referenced above use their bit lines both for the write and read operations for the search-and-compare operations. Such an arrangement places some constraint on the overall operational speed of the CAM cell array. This problem can be alleviated by using search lines for carrying the search data during a search-and-compare operation while using the bit lines only for the write and for the read operations, such as the design published by Bergh et al. in: “A fault-tolerant associative memory with high-speed operation”, IEEE Journal on Solid-State Circuits SC-25 (1990), 912-919. This design uses a static memory which is again limited to a binary storage capability. Futhermore, the seach lines in this design are connected to the source or drain terminals of the comparison circuit, causing a heavy loading on the search line thereby causing a relatively high power consumption, and a slower search-and-compare operation.
In view of the above, there is clearly a need for a CAM cell configuration that demands relatively lower power consumption, offers a relatively faster search-and-compare operation with a relatively more stable match line voltage and bit line capacitance, while providing a ternary storage capability.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a improved dynamic content addressable memory (CAM) cell suitable for constructing relatively high-speed and large-capacity CAM arrays, having binary and ternary storage capability.
In accordance with a first aspect of the present invention, there is provided a content addressable memory. The content addressable memory includes at least two pairs of bitlines coupled to opposite sides of at least two sense amplifiers in an open bitline configuration. Each bitline of each pair of bitlines is coupled to one of the at least two sense amplifiers, and plurality of ternary dynamic content addressable memory cells are coupled to each of the at least two pairs of bitlines.
In a presently preferred embodiment of the present invention, the at least two pairs of bitlines on each side of the at least two sense amplifier are of equal length

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