Dynamic comparator with improved pre-charge/set-up time

Details Dynamic comparator with improved pre-charge/set-up time Dynamic comparator with improved pre-charge/set-up time

1997-07-31

1999-02-16

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 64, 327 65, 3401462, 36518907, H03K 522

Patent

active

058724672

ABSTRACT:
A multiple bit dynamic comparator is described which includes logic gates that function to turn-off particular devices that are directly connected to the comparator output node and thereby isolate the output node from parasitic capacitances during a pre-charge/set-up phase. During the pre-charge/set-up phase, the output node is charged to VCC and the input signals to be compared are applied to the appropriate inputs of a plurality of comparison sub-circuits. The plurality of comparison subcircuits are coupled to the output node. Each device within the comparison sub-circuits that is directly connected to the output node of the dynamic comparator (i.e. top row of devices) has its gate coupled to a NOR gate. The inputs of the NOR gate are cross-coupled to input signals being compared such that when a match occurs between the inputs the NOR gates hold all top row devices off. As a result, the pre-charging of the output node during the pre-charge phase is unaffected by unwanted parasitic capacitances.

REFERENCES:
patent: 5617348 (1997-04-01), Maguire
patent: 5694362 (1997-12-01), Zhang et al.
patent: 5729190 (1998-03-01), Iyengar et al.
patent: 5754463 (1998-05-01), Henstrom et al.
patent: 5761140 (1998-06-01), Choi
patent: 5764089 (1998-06-01), Partovi et al.

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