Boots – shoes – and leggings
Patent
1983-12-23
1986-02-04
Anagnos, Larry N.
Boots, shoes, and leggings
307452, 307481, H03K 19017, H03K 19096
Patent
active
045690324
ABSTRACT:
A dynamic CMOS logic circuit for computing multiple AND functions contains a sequence of at least three successive stages controlled by the same timing signal, each stage having a logic network of driver transistors in which at most three such transistors are connected in series along any path through the network.
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Goncalves et al., "A Racefree-Dymamic CMOS Technique for Pipelined Logic Structures"; Digest of European Solid State Circuits Conference; Jul. 1982; pp. 141-144.
C. Mead et al., Introduction to VLSI Systems, "1.11 Delays in Another form of Logic Circuitry," Addison-Wesley Publishing Company, 1980, pp. 22-23.
H. Taub, Digital Circuits and Microprocessors, "5.10 The Look-Ahead Carry Adder," McGraw-Hill Book Company, 1982, pp. 205-209.
R. H. Krambeck et al., "High-Speed Compact Circuits with CMOS", IEEE Journal of Solid-State Circuits, vol. SC-17, No. 3, Jun. 1982, pp. 614-619.
C. M. Lee et al., "Current Status and Future Projection of CMOS Technology," Computer Networks, Proceedings of the 25th IEEE Computer Society International Conference", (CompCon 82), Washington, D.C., Sep. 1982, pp. 716-719.
Anagnos Larry N.
AT&T Bell Laboratories
Caplan David I.
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