Dynamic CMOS current surge control

Details Dynamic CMOS current surge control Dynamic CMOS current surge control

1987-02-04

1988-04-05

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 307605, 307452, 307279, 377105, 377106, 364707, G06F 104, G06F 922

Patent

active

047361190

ABSTRACT:
Integrated circuits having a large number of transmission gate logic stages have been found to draw a large current surge on power-up. This is due to the floating input node of complementary inverters causing current to flow briefly before clock pulses arrive. The present invention provides a DC voltage on the gates of the pass transistors until the system clock pulses arrive, thereby eliminating the floating node. An optional periodic window may be generated to examine the system clock after power-up, to detect a loss of clock condition.

REFERENCES:
patent: 4317180 (1982-02-01), Lies
patent: 4554465 (1985-11-01), Koike
patent: 4570219 (1986-02-01), Shibukawa et al.
patent: 4606053 (1986-08-01), Schroder
patent: 4641044 (1987-02-01), Shiraishi
patent: 4686386 (1987-08-01), Tadao
patent: 4694196 (1987-09-01), Hasley et al.
patent: 4694197 (1987-09-01), Sprague
patent: 4700084 (1987-10-01), Honaker, Jr.

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