Dynamic CMOS buffer for low current switching

Details Dynamic CMOS buffer for low current switching Dynamic CMOS buffer for low current switching

1988-06-17

1989-10-24

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307452, 307481, 307572, 307576, 3072965, 3072966, H03K 1716, H03K 19094, H03K 301

Patent

active

048764655

ABSTRACT:
A sense circuit for sensing the transition of an input signal from a first logic state to a second logic state and making a corresponding logic transition on the output at a higher slew rate includes a first buffer stage having a complementary pair of transistors consisting of P-channel transistor (34) and N-channel transistor (32) having the drains thereof isolated by N-channel transistor (26). A precharge signal is connected to the gates of the transistors (34) and (32) to turn on transistor (32) and pull the drain thereof low. The drain of transistor (32) is connected to the gate of N-channel transistor (36). The P-channel transistor (26) is connected to an input signal and is operable to connect the drain of transistor (34) to the gate of transistor (36) when transistor (32) is turned off. This results in a node (38) being pulled from a high logic voltage to a low logic voltage when the input signal falls one V.sub.T below the source of transistor (26).

REFERENCES:
patent: 4700086 (1987-10-01), Ling et al.

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