Dynamic clocking system using six clocks to achieve six delays

Details Dynamic clocking system using six clocks to achieve six delays Dynamic clocking system using six clocks to achieve six delays

1982-03-01

1986-01-21

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307453, 307602, 307603, 307605, H03K 19096, H03K 5135, H03K 5153

Patent

active

045659346

ABSTRACT:
A dynamic metal oxide semiconductor field effect transistor clocking circuit that includes a first circuit which in turn includes a chargeable node, precharge capability, isolation capability and discharge capability to provide an output upon the occurrence of an input. This first circuit is connected to a second circuit which also includes a chargeable node, a precharge capability, isolation capability and the first circuit discharge capability to conditionally provide a total circuit delay output upon an occurrence of an input from the first circuit with a minimum number of clocking signals.

REFERENCES:
patent: 3497715 (1970-02-01), Yen
patent: 3601627 (1971-08-01), Booher
patent: 3609392 (1971-09-01), Tetik
patent: 3617767 (1971-11-01), Booher
patent: 3676709 (1972-07-01), Ducamus et al.
patent: 4049979 (1977-09-01), Shieu et al.
patent: 4259595 (1981-03-01), Omori

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