Dynamic clock switching circuitry and method

Details Dynamic clock switching circuitry and method Dynamic clock switching circuitry and method

1993-05-13

1996-05-14

Kriess, Kevin A.

Pulse or digital communications

Repeaters

Testing

375357, 375356, 327141, 327156, 327281, H04L 700, H03K 5135

Patent

active

055176380

ABSTRACT:
Circuitry for switching between a first and second clock signal is provided having a first local clock circuit 202, a first synchronizing circuit 200 connected to said first clock circuit 202, a first delay circuit 206a-d connected to said first synchronizing circuit 200 and said first clock circuit 202, a second delay circuit 206e, 210, connected to said first delay circuit 206a-d and said first clock circuit 202, a first logic circuit 220 connected to said first 206a-d and second 206e, 210 delay circuits and said first synchronizing circuit 200, a second local clock circuit 102, a second synchronizing circuit 100 connected to said second clock circuit 102, a third delay circuit 106, 108, 110, connected to said second synchronizing circuit 100 and said second clock circuit 102, a second logic circuit 104 connected to said second clock circuit 102 and a portion of said third delay circuit 106, 108, 110, a third logic circuit 120 connected to said third delay circuit 106, 108, 110, and said second clock circuit 102, and a multiplexer 16 connected to said first 220 and third 120 logic circuits. The method of the present invention switches between a first 19 and second 21 clock signal by detecting a change in a signal 23 indicative of need to switch from said first clock signal to said second clock signal (or vice vers. a) 302, generating at least one local control signal 70, 72 responsive to said detection 304, deselecting a first in use clock signal 306 responsive to a first local control signal, selecting the second clock signal 308 for use responsive to a second local control signal, and switching to the non-used (second) clock signal after a preselected delay 310 based upon said second clock signal and said detection of said change in said signal.

REFERENCES:
patent: 4398155 (1983-08-01), Atwell, Jr. et al.
patent: 4511993 (1985-04-01), Bromme et al.
patent: 4651103 (1987-03-01), Grimes
patent: 4696019 (1987-09-01), Tulpule et al.
patent: 4823262 (1989-04-01), Calle
patent: 4841523 (1989-06-01), Roffinella et al.
patent: 4866703 (1989-09-01), Black et al.
patent: 4870299 (1989-09-01), Chen
patent: 5241543 (1993-08-01), Amada et al.
patent: 5274678 (1993-12-01), Ferolito et al.
patent: 5287025 (1994-02-01), Nishimichi

Affiliated with

Also associated with

Rating

Dynamic clock switching circuitry and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic clock switching circuitry and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic clock switching circuitry and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1904265