Dynamic bus locking in a cross bar switch

Details Dynamic bus locking in a cross bar switch Dynamic bus locking in a cross bar switch

1998-08-19

2001-11-27

Horabik, Michael (Department: 2735)

Communications: electrical

Selective

Decoder matrix

C340S002100, C709S209000, C709S213000, C710S120000, C710S120000, C710S200000

Reexamination Certificate

active

06323755

ABSTRACT:

FIELD OF INVENTION
The present invention relates to bus arbitration in computer systems, and more specifically to bus locking in a cross-bar switch.
BACKGROUND
Significant advances in silicon densities have allowed for the integration of many functions onto a single silicon chip. With this increased density, many of the peripherals in a computer system that were normally attached to the processor via an external bus now are attached via an on-chip bus. In addition, the bandwidth requirements of these on-chip buses are increasing due to the integration of various audio, video, and graphic functions along with the processor. As a result, providing maximum on-chip bus performance is desired.
FIG. 1
illustrates a conventional on-chip bus architecture
100
, containing an on-chip bus
120
and bus arbiter
140
. The on-chip bus
120
supports read and write data transfers between master devices
110
and slave devices
130
equipped with an on-chip bus interface. A “master” device is one which requests access to or control of the on-chip bus
120
and transmits and receives data across the on-chip bus
120
. A “slave” device is one which transmits or receives data across the on-chip bus
120
and is responsive to a master. The slave may not request access to or control of the on-chip bus
120
. Access to the on-chip bus
120
is granted through an arbitration mechanism
140
, or arbiter, which is attached to the on-chip bus
120
and prioritizes all transfer requests from masters devices for bus ownership. Timing for all on-chip bus signals is provided by a single clock source (not shown). This single clock source is shared by all master devices and slave devices attached to the on-chip bus
120
. The master device may operate at a different (higher) frequency. Synchronization logic may be implemented at the interface of the two clock domains.
One approach to maximizing the performance of the on-chip bus is to use multiple parallel high speed master and slave buses instead of a single bus as illustrated in
FIG. 1. A
mechanism, such as a cross-bar switch, is typically used to allow these buses to communicate with each other. Under conventional protocols, a master device may initiate a bus lock data transfer request which locks the bus from access by other master devices until the master device releases the bus. The release of the bus by the master device occurs when the master device which initiated the bus lock transfer, releases the bus. However, with a multiple parallel bus architecture, all slave buses would be locked during a bus lock transfer. While locked, these slave buses are allowed only to service requests from the master device which initiated the bus lock transfer, regardless of whether or not a slave bus is actually needed to service these requests. This results in increased latency for other master devices to gain access to the locked slave bus.
Accordingly, there exists a need for a method and system for providing a mechanism which has the capability of selectively locking slave buses during a bus lock transfer in a on-chip bus architecture with multiple parallel high speed buses. Such selective locking will allow only buses actually needed to service a master device's bus lock transfer to be locked while leaving the remainder of the slave buses free to service requests from other master devices. This method should minimize the latency between data transfers. The present invention addresses such a need.
SUMMARY
The present invention provides a cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus ports, the slave bus ports adapted to receive a plurality of slave buses; switching mechanism for selectively coupling the plurality of master bus ports to the plurality of slave bus ports; and a configuration mechanism for locking at least one of the plurality of slave buses in response to a transfer request initiated by a master device attached to one of the plurality of master buses. The cross-bar switch of the present invention has the capability of selectively locking slave buses during a bus lock transfer. In the preferred embodiment, the configuration mechanism is a Bus Lock Bit on Configuration Registers on the cross-bar switch. The Bus Lock Bit is programmable through the Device Control Register bus, which is separate from the on-chip buses, which allows the cross-bar switch of the present invention to be dynamically programmable and changed by a processor in a larger system. The cross-bar switch of the present invention minimizes the latency between data transfers. This improves the bandwidth and throughput on the on-chip bus.


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