Dynamic bus arbitration with concurrent same bus granting every

Details Dynamic bus arbitration with concurrent same bus granting every Dynamic bus arbitration with concurrent same bus granting every

1992-02-21

1993-03-16

Shaw, Dale M.

395200, 395275, G06F 1318, G06F 1328

Patent

active

051951851

ABSTRACT:
Apparatus and method for optimizing bus arbitration during direct memory access (DMA) data transfers across a nondedicated bus between a memory and/or a plurality of external devices each master having an arbitration priority. At least two nonoverlapping clocks are provided per transfer cycle and there is at least one transfer cycle per arbitration cycle. Arbitration priority requests are transmitted from each external device to an arbitration bus only at the rise of the first clock. At the end of the last clock, the priority code of the external device having the highest priority is determined to designate the external device which is to become bus master. Addresses and data are transferred between the designated bus master and the memory or another of the external devices via the nondedicated bus during the next cycle after a then active bus master relinquishes control. The priorities of the external devices can be changed dynamically. Arbitration cycles are pipelined in such manner that there is no loss of address or data transfer cycles. The then active bus master may extend the number of cycles during which it communicates with one or more external devices. A device designated as next in line as bus master may be preempted under a certain condition.

REFERENCES:
patent: 4453211 (1984-06-01), Askinazi et al.
patent: 4481580 (1984-11-01), Martin et al.
patent: 4837677 (1989-06-01), Burrus, Jr. et al.
patent: 4924427 (1990-05-01), Savage et al.
patent: 4947368 (1990-08-01), Donaldson et al.
patent: 4949301 (1990-08-01), Joshi et al.
patent: 4967344 (1990-10-01), Scavezze et al.
patent: 4987529 (1991-01-01), Craft et al.
patent: 5001625 (1991-03-01), Thomas et al.
patent: 5006982 (1991-04-01), Ebersole et al.
patent: 5016162 (1991-05-01), Epstein et al.
patent: 5043937 (1991-08-01), Glaise et al.
IBM Microchannel Architecture Supplement for the PS/2 Hardware Interface Technical Reference, Nov. 1989, pp. 30-33.
Intro. to VLSI Systems, Mead & Conway, Addison-Wesley, 1980.

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