Dynamic burst control for data transfers

Details Dynamic burst control for data transfers Dynamic burst control for data transfers

1988-04-07

1991-03-05

Fleming, Michael R.

Boots, shoes, and leggings

364900, 3642428, 3642412, 364260, 3642383, 364941, 364940, 36492693, G06F 1300

Patent

active

049981986

ABSTRACT:
In a data processing system, a device controller, configured to control data transfers between a processor unit and a peripheral device on an input/output bus, is provided with apparatus that permits a data transfer cycle to continue until all data has been transferred, or to allow for interruption of the data transfer cycle by another device controller requesting access to the input/output via a request signal. During a data transfer cycle the apparatus resonds to detection of the request signal to interrupt the data transfer cycle after a predetermined number of data words are transferred, permitting access to the input/output bus for other of the device controllers. In absence of the request signal, the apparatus permits the data transfer to continue until all data has been transferred between the peripheral device and the processor unit.

REFERENCES:
patent: 4383295 (1983-05-01), Miller et al.
patent: 4484271 (1984-11-01), Miu et al.
patent: 4719622 (1988-01-01), Whipple et al.
patent: 4736291 (1988-04-01), Jennings et al.
patent: 4760515 (1988-07-01), Malmguist et al.
patent: 4831523 (1989-05-01), Lewis et al.

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