Dynamic biasing techniques for low power pipeline analog to...

Details Dynamic biasing techniques for low power pipeline analog to... Dynamic biasing techniques for low power pipeline analog to...

2001-08-31

2002-10-08

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S122000

Reexamination Certificate

active

06462695

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
NOT APPLICABLE
STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
NOT APPLICABLE
REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAM LISTING APPENDIX SUBMITTED ON A COMPACT DISK.
NOT APPLICABLE
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuits. More particularly, embodiments of the invention relate to a method and circuitry for implementing low-power pipeline analog-to-digital converter circuits.
Pipeline analog-to-digital converters (ADC) are used in high-performance operations, such as in high-speed, high-resolution data acquisition systems.
An ADC can have many residue amplifiers. Most of the power dissipation of an ADC occurs in the residue amplifiers. Such amplifiers are typically class-A type op-amps and thus dissipate significant power. Because one of the primary goals of many ADC circuits is to achieve high-speed, many ADCs are not designed for low-power dissipation. However, the growing use of ADCs in battery powered systems requires the minimization of power dissipation.
“A 16-mW, 120-dB Linear Switched-Capacitor Delta-Sigma Modulator with Dynamic Biasing,” by Dan B. Kasha, Wai L. Lee, and Axel Thomsen describes a dynamic biasing technique. However, this biasing technique is not used in a pipeline ADC but rather is used in a different type of ADC circuit which is a fourth-order delta-sigma (&Dgr;&Sgr;) ADC. The problem with this design is that its biasing circuit requires many elements. If applied to a pipeline ADC, the power consumed by the total number of elements of the biasing circuit will be multiplied by the number of stages in the pipeline ADC. As a result, low-power dissipation would not be achieved.
Thus, there is a need for a new amplifier circuit for pipeline ADC circuits. The circuit should achieve low-power dissipation.
BRIEF SUMMARY OF THE INVENTION
The present invention achieves the above need with a method and circuitry for implementing an ADC. More particularly, embodiments of the present invention provide dynamic biasing methods and circuitry that achieves a low-power pipeline ADC.
Embodiments of the present invention provide an amplifier circuit for pipeline ADCs having multiple stages. In an N-bit ADC system, there will be (N−2) stages of pipeline formed by residue amplifiers and one final 2-bit flash converter stage. In one embodiment of the present invention, specifically for a 12-bit ADC, there are
10
residue amplifier based stages and one final 2-bit flash converter stage, as shown in FIG.
1
. The pipeline ADC system makes use of &phgr;
A
and &phgr;
B
clocks shown in
FIG. 2
, both having a 50% duty cycle to operate these stages. Each stage performs a sample function for one-half the clock period and later performs a residue amplification and hold function for the other half of the clock period. At any given time, half of the pipeline stages are in sample mode and other half of pipeline stages are in hold mode, in alternating manner. The stages include residue amplifiers which include a pre-amp and a class-A type output stage which uses a current source. Most of the residue amplifier power is expended in the output stage due to the current source. The current source is turned off during the sample mode. Some embodiments include a second current source that provides a bleeder current during the sample phase so that the pre-amp remains in steady state.
In one embodiment of the present invention provide a gain stage configured to receive and digitize a signal, and to amplify and output a residue with a gain. Also included is an output stage coupled to the gain stage and configured to bias the gain stage. The output stage includes a current source and a driver transistor. The current source is on during a hold mode and off during a sample mode whereby the overall power dissipation of the output stage is reduced.
This reduction in power can occur in all residual amplifiers of a pipeline ADC to which the invention is applied. Because at least one half of all the residual amplifiers in the pipeline ADC will be in sample mode at any given time, significantly less power is dissipated in the overall system.
In one embodiment, the amplifier circuit includes a second current source. The second current source is configured to bias the gain stage during both the hold mode and the sample mode so that the gain stage remains in steady state during the hold and sample modes.
In another embodiment, the current source has a bias transistor with a gate coupled to a switch. The switch turns the bias transistor on during the hold mode and off during the sample mode. Accordingly, the current source turns on during the hold mode and off during the sample mode.
In another embodiment, the current source is controlled by a master bias controller.
Embodiments of the present invention achieve their purposes and benefits in the context of known circuit and process technology and known techniques in the electronic and process arts. Further understanding, however, of the nature, objects, features, and advantages of the present invention is realized by reference to the latter portions of the specification, accompanying drawings, and appended claims. Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description, accompanying drawings, and appended claims.


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Abo, Andrew M., et al., “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999.
Nakamura, K., et al., “A CMOS Analog Front End Chip-Set for Mega Pixel Camcorders,” 2000 IEEE International Solid-State Circuits Conference, pp. 190-191, 2000.
Kasha, Dan B. et al., “A 16-mW, 120-dB Linear Switched-Capacitor Delta-Sigma Modulator with Dynamic Biasing,” IEEE Journal of Solid-State Circuits, vol. 34, No. 7, pp. 921-925, Jul. 1999.
Lewis, Stephen H., “Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-Rate Applications,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, No. 8, pp. 516-523, Aug. 1992.

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