Dynamic and adaptive optimization of read compare levels...

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185190, C365S185240, C365S189070, C365S189040

Reexamination Certificate

active

07957187

ABSTRACT:
A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points.

REFERENCES:
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patent: 7181565 (2007-02-01), Surico
patent: 7315917 (2008-01-01), Bennett
patent: 2007/0217258 (2007-09-01), Wang
patent: 2008/0263266 (2008-10-01), Sharon
patent: 2008/0285351 (2008-11-01), Schlick
Murin, et al., U.S. Appl. No. 12/111,729, filed Apr. 29, 2008, “Method for Adaptive Setting of State Voltage Levels in Non-Volatile Memory,”.

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