Dynamic address translation allowing quick update of the change

Details Dynamic address translation allowing quick update of the change Dynamic address translation allowing quick update of the change

1992-09-02

1996-03-05

Whitfield, Michael A.

Boots, shoes, and leggings

364DIG1, 395416, G06F 1210

Patent

active

054974690

ABSTRACT:
A dynamic address translation processing apparatus in a data processing system having a main memory for storing an address conversion table, and a central processing unit for converting a virtual address to a real address by referring the address conversion table. The central processing unit includes a first register for holding the virtual address, a second register for holding a table entry of the address conversion table corresponding to the virtual address held in the first register and, having an update bit indicative that a page in memory has been written to a third register for holding the real address of the table entry held in the second register, a comparison circuit for comparing the virtual address held in the first register with the other virtual address to be converted to the real address, and an update unit for updating the update bit in the table entry held in the second register. When the virtual address coincides with the other virtual address in the comparison circuit, the table entry converted by the update unit is written into an address of the main memory held in the third register.

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Research Disclosure, No. 299, Mar. 1989, Havant, GB, XP52970, "Separate Look-Aside Buffer Change Bit Array," p. 2244.

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