Dynamic adder with reduced logic

Details Dynamic adder with reduced logic Dynamic adder with reduced logic

2006-08-01

2006-08-01

Chaki, Kakali (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07085796

ABSTRACT:
A dynamic parallel adder is provided which eliminates the positive (or negative) complimentary carry generate and propagate signal logic normally used to implement a conventional dynamic parallel added. The method for implementing the incentive adder users a novel XOR configuration constructed with dynamic CMOS logic circuits.

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R.P. Brent et al., “A Regular Layout for Parallel Adders,” IEEE Transactions on Computers, vol. C-31, No. 3, p. 1-9, Mar. 1982.

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