Dynamic 3-level partial result merge adder

Details Dynamic 3-level partial result merge adder Dynamic 3-level partial result merge adder

1998-12-11

2001-12-25

Mai, Tan V. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S670000

Reexamination Certificate

active

06334136

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital computing, and more particularly to an apparatus and method for a three logic-level 32-bit adder/subtractor that implements carry-propagate logic and that allows a subset of the contents of the register containing one of the 32-bit operands to be modified while leaving the remainder of the register contents unmodified.
2. Description of the Related Art
Two areas of related art are relevant to the present invention. One area of related art is the prior art x86 instruction set regarding addition and subtraction, and the manner in which the x86 instruction set's manipulation of registers must be altered to support pipelining. The other area of related art is the N-nary logic design style. These two areas of prior art are discussed separately below.
x86 Instruction Set's Manipulation of Registers
The original 8086 instruction set supported eight 16-bit general purpose registers that could be used, among other purposes, for addition and subtraction operations. Each addition or subtraction instruction requires two operands, which are stored in registers for use by the adder/subtractor. The nomenclature “X” came to represent a standard 16-bit register. Four 8086 registers of interest were therefore known as “AX”, “BX”, “CX”, and “DX”. These four standard registers AX, BX, CX, DX are of interest in the background discussion of the present invention because the 8086 instruction set supported a conceptual division of such registers into two constituent parts each.
The 8086 standard registers were conceptually divided into a low byte and a high byte, wherein the low byte is identified by the “L” nomenclature and the high byte is identified by the “H” nomenclature. The standard registers AX, BX, CX, and DX therefore conceptually further comprised “AH” and “AL”, “BH” and “BL”, “CH” and “CL”, and “DH”and “DL”, respectively. This division of registers AX, BX, CX, and DX allowed byte-access (8-bit access) to the upper (“H”) and lower (“L”) bytes of these registers for purposes of performing addition and subtraction operations.
With the introduction of the 386, the x86 architecture grew to support 32-bit registers, known as extended registers and denoted by the nomenclature “ExX”. Despite this introduction of extended registers, the 386 was required to support older code that had been written for 16-bit registers. The need to support both a 32-bit and a 16-bit instruction set led to a conceptual overlay structure of extended registers. The overlay structure for extended registers defines a standard 16-bit register (i.e., AX) to occupy the 16 least significant bits of the corresponding extended register (i.e., EAX), with a low byte (i.e., AL) occupying bits
0
through
7
of both the standard and extended registers, and with a high byte (i.e., AH) occupying bits
8
through
15
of the standard and extended registers. This overlay structure is illustrated in FIG.
11
A.
FIG. 11A
illustrates that each extended register EX comprises a top portion (bits
16
-
31
), denoted in
FIG. 11A
with a “T”, and a standard register portion (bits
0
-
15
), denoted in
FIG. 11A
with an “X”.
FIG. 11A
further illustrates that the standard register portion X further comprises a high byte H and a low byte L. Such overlay structure allows, for each add or subtract instruction, the option of utilizing one of four register sizes for the operands: a 32-bit extended register, a 16-bit standard register, an 8-bit high byte, or an 8-bit low byte.
N-nary Logic
A second area of interest regarding the background of the present invention deals with the manner in which addition and subtraction operands are represented when they are stored in the registers discussed above. Most computer systems represent addition and subtraction operands and results as binary numbers. In systems using traditional binary logic, the truth table for one-bit addition is set forth in Table 1.
TABLE 1
A
B
A + B
0
0
0
0
1
1
1
0
1
1
1
 0*
In the last row of Table 1, a carry condition occurs. That is, the result is 0, but a carry into the next-higher-order bit position, corresponding to a decimal value of 2, has conceptually occurred. In addition to single bits, the addition operation may be performed on multiple bits, including addition of two two-bit values. The truth table for such an operation is set forth in Table 2, where the first operand A is a two-bit value comprising bits A
0
and A
1
. The second operand, B, is a two-bit value comprising bits B
0
and B
1
.
TABLE 2
A =
B =
A + B =
Decimal
Decimal
Dec.
A
1
A
0
B
1
B
0
Value
Value
A + B
Value
0
0
0
0
0
0
00
0
0
0
0
1
0
1
01
1
0
0
1
0
0
2
10
2
0
0
1
1
0
3
11
3
0
1
0
0
1
0
01
1
0
1
0
1
1
1
10
2
0
1
1
0
1
2
11
3
0
1
1
1
1
3
 00*
0
1
0
0
0
2
0
10
2
1
0
0
1
2
1
11
3
1
0
1
0
2
2
 00*
0
1
0
1
1
2
3
 01*
1
1
1
0
0
3
0
11
3
1
1
0
1
3
1
 00*
0
1
1
1
0
3
2
 01*
1
1
1
1
1
3
3
 10*
2
Each output value in the “A+B” column of Table 2 indicated with an asterisk denotes a carry condition where a logical one has conceptually carried into the next-higher-order bit (the bit position corresponding to a decimal value of four).
In contrast to the binary system discussed above, the present invention utilizes an N-nary logic representation. The N-nary logic family supports a variety of signal encodings, including 1-of-4. The N-nary logic family is described in a copending patent application, U.S. patent application Ser. No. 09/019,355, filed Feb. 5, 1998, now U.S. Pat. No. 6,066,965, and titled “Method and Apparatus for a N-Nary logic Circuit Using 1-of-4 Signals”, which is incorporated herein for all purposes and is hereinafter referred to as “The N-nary Patent.” This application also incorporates several other copending patent applications, including U.S. patent application Ser. No. 09/179,330, filed Oct. 27, 1998, entitled “Method and Apparatus for Logic Synchronization,” now U.S. Pat. No. 6,118,304, and U.S. patent application Ser. No. 09/206,463, filed Dec. 7, 1998, titled “Method and Apparatus for 3-stage 32-Bit Adder/Subtractor,” hereinafter referred to as the “Adder Patent,” all of which are incorporated by reference into this application.
In 1-of-4 encoding, four wires are used to indicate one of four possible values. In contrast, traditional static logic design uses two wires to indicate four values, as is demonstrated in Table 2. In Table 2, the A
0
and A
1
wires are used to indicate the four possible values for operand A: 00, 01, 10, and 11. The two B wires are similarly used to indicate the same four possible values for operand B. “Traditional” dual-rail dynamic logic also uses four wires to represent two bits, but the dual-rail scheme always requires two wires to be asserted. In contrast, N-nary logic only requires assertion of one wire. The benefits of N-nary logic over dual-rail dynamic logic, such as reduced power and reduced noise, should be apparent from a reading of The N-nary Patent.
All signals in N-nary logic, including 1-of-4, are of the 1-of-N form where N is any integer greater than one. A 1-of-4 signal requires four wires to encode four values (
0
-
3
inclusive), or the equivalent of two bits of information. More than one wire will never be asserted for a 1-of-N signal. Similarly, N-nary logic requires that a high voltage be asserted for all values, even 0. (Some versions of N-nary logic allow a “null” case, where no high voltage is asserted for an N-nary signal, which indicates that the N-nary signal has not yet evaluated, and is not required).
Any one N-nary gate may comprise multiple inputs and/or outputs. In such a case, a variety of different N-nary encodings may be employed. For instance, consider a gate that comprises two inputs and two outputs, where the inputs are a 1-of-4 signal and a 1-of-2 signal and the outputs comprise a 1-of-4 signal and a 1-of-3 signal. Various variables, including P, Q, R, and S, may be used to describe the encoding for these inputs and outputs. One may say that one in

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