Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-04-05
2002-01-29
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S014000, C438S016000, C438S108000, C228S105000
Reexamination Certificate
active
06342400
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for testing the integrity of soldered joints in semiconductor package assemblies. The present invention has particular applicability in testing the joint adhesion of fine-pitched ball grid array (FBGA) packages to a substrate.
BACKGROUND ART
In conventional electronic circuit board assembly techniques known as “solder bumping”, the circuit board, such as a laminated printed circuit board (PCB), is provided with an array of bonding pads, such as fine-pitched round metal bonding pads, and a packaged semiconductor device, such as an integrated circuit in a molded plastic package known as a fine-pitched ball grid array (FBGA), is provided with a corresponding array of comparably sized and shaped bonding pads. A solder preform called a “solder ball” is placed between each of the bonding pads of the circuit board and a corresponding bonding pad of the semiconductor device, and then the assembly is heated, as in an oven, to melt (or “reflow”) the solder balls, each of which adhere to its respective pair of bonding pads to establish electrical contact between the circuit board and the semiconductor device, and to hold the semiconductor device in place on the circuit board.
Due to the limitations of the solder bumping process, one or more of the solder balls occasionally do not wet properly to their bonding pads during reflow, resulting in cracks in the joint between those solder bumps and the improperly-wetted bonding pads. Cracks also occur during stress testing (i.e., heat cycling) of the assembled circuit board. Cracks are disadvantageous to the extent they result in partial or completely open circuits, and consequent failure of the assembled board. Therefore, the quality of the solder bumping process is typically monitored to detect cracks. Conventional inspection techniques involve cross-sectioning an assembled circuit board. However, this method has drawbacks, in that it is time-consuming and does not test all bonds to determine solder bump bond strength. Furthermore, other conventional inspection techniques involving acoustic microscopy and x-rays cannot detect cracks.
There exists a need for an accurate, low-cost methodology for inspection of all the solder joints of solder-bumped circuit board assemblies.
SUMMARY OF THE INVENTION
An advantage of the present invention is an accurate and reliable method of inspecting all the solder joints of a semiconductor package assembly.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of inspecting solder joints of a semiconductor package assembly, the package assembly comprising a substrate with bonding pads, a semiconductor device with bonding pads, and solder bumps attached between each substrate bonding pad and a corresponding bonding pad of the semiconductor device, the method comprising immersing the package assembly in a solution comprising dye; placing the immersed package assembly under a vacuum such that, when cracks exist between the solder bumps and substrate bonding pads, or between the solder bumps and the semiconductor device bonding pads, the dye solution flows into the cracks; removing the package assembly from the vacuum and the dye solution; drying the package assembly; separating the semiconductor device and the substrate to expose a plurality of the substrate bonding pads or the semiconductor device bonding pads; and inspecting the exposed bonding pads for the dye, thereby locating the cracks.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 4230754 (1980-10-01), Maher et al.
patent: 5651493 (1997-07-01), Bielick et al.
patent: 6117352 (2000-09-01), Weaver et al.
patent: 6117695 (2000-09-01), Murphy et al.
Levis et al., Assembly and Solder Joint Reliability of Plastic Ball Grid Array with Lead-Free Versus Lead-Tin Interconnect, 2000 Electronic Components and Technology Conference, pp 1198-1204.
Advanced Micro Devices , Inc.
Elms Richard
McDermott & Will & Emery
Pyonin Adam
LandOfFree
Dye penetrant test for semiconductor package assembly solder... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dye penetrant test for semiconductor package assembly solder..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dye penetrant test for semiconductor package assembly solder... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2863212