Duty-ratio correction circuit and clock generation circuit

Details Duty-ratio correction circuit and clock generation circuit Duty-ratio correction circuit and clock generation circuit

1999-02-09

2001-03-06

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S170000, C327S153000, C327S155000, C327S298000, C327S536000

Reexamination Certificate

active

06198322

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PLL or DLL circuit, especially to a circuit for controlling a duty ratio of a signal.
2. Description of the Background Art
When an input clock signal having a high period/low period ratio or duty ratio of one to one is fed to a circuit, the duty ratio may deviate from 1:1 inside the circuit, for example, due to the level of the input clock signal or the characteristics of an input buffer. Further, in some cases, the duty ratio of the input clock signal which is generated in the PLL or DLL circuit may not be 1:1 due to imperfect oscillation characteristics of a voltage controlled oscillator or a delay stage.
With the duty ratio of other than 1:1, a problem will arise, for example, when both rising and falling edges of the input clock signal are used as timing signals for the operation of logic elements in the circuit. More specifically, the deviation of the duty ratio from 1:1 increases the risk that a time when an element starts its operation at the rising edge may coincide with a time when the element starts its operation at the falling edge. This causes a shortage of timing margins.
FIG. 13
shows circuitry for correcting the duty ratio of the clock signal to 1:1, which resolves the above problem. This circuitry is designed to incorporate a duty-ratio correction circuit DRC
3
into a well-known PLL circuit PLL
1
, disclosed for example in R. Bhagwan and A. Rogers, “A 1 GHz Dual-Loop Microprocessor PLL with Instant Frequency Shifting”, ISSCC Digest of Technical Papers, pp. 336-337, February, 1997.
First, we will describe the operation of the PLL circuit PLL
1
. An input clock signal S
1
and a feedback clock signal S
2
are frequency-divided by frequency dividers CD
1
and CD
2
, respectively, and fed to a phase-frequency detector
6
. The phase-frequency detector
6
detects a coincidence or phase difference between those signals and outputs a signal S
3
for indicating the intensity of voltage which is responsive to the detection result, to a charge pump
7
. Converting the signal S
3
into a current signal S
4
, the charge pump
7
acts as a charge supply source for a loop filter
8
. The loop filter
8
includes a capacitor C
3
whose one end is connected to a power source VDD (showing the potential at that end also as “VDD”), so the potential of the other end is smoothed to be a signal S
5
to a voltage controlled oscillator
5
. The signal S
5
varies an oscillation period and a phase of a signal S
6
output from the voltage controlled oscillator
5
.
In a standard PLL circuit, the signal S
6
directly becomes the feedback clock signal S
2
. In the circuitry in
FIG. 13
, on the other hand, the signal S
6
is fed to the duty-ratio correction circuit DRC
3
. Then, a signal S
7
outputted from the duty-ratio correction circuit DRC
3
becomes the feedback clock signal S
2
through a buffer B
1
.
Next, we will describe the duty-ratio correction circuit DRC
3
. The duty-ratio correction circuit DRC
3
consists of a level shifting circuit LS
1
, a duty-ratio detecting circuit
2
, and a duty-ratio correction filter
3
.
The level shifting circuit LS
1
varies a threshold value of the signal S
6
for determining the transition timing of the signal S
7
. By using the level shifting circuit LS
1
, the threshold value can be shifted from an intermediate value between high and low which is usually used as a threshold voltage. Thus, the duty ratio of the signal S
6
becomes variable.
FIG. 14
is a timing chart of the operation of the level shifting circuit LS
1
. It shows waveforms S
7
a
, S
70
, and S
7
b
of the signal S
7
when a threshold value Vref of the signal S
6
is Vrefa, Vref
0
, and Vrefb, respectively, where Vrefa<Vref
0
<Vrefb.
As shown in
FIG. 14
, a rising edge of the signal S
7
becomes earlier and a falling edge thereof becomes later with the decrease in the threshold value Vref. That is, a high period of the signal S
7
increases. On the other hand, a low period of the signal S
7
increases as the threshold value Vref increases.
The duty-ratio detecting circuit
2
is a charge pump for converting the signal S
7
into a current signal S
8
, and the duty-ratio correction filter
3
is a filter including a capacitor C
2
whose one end is grounded (showing the potential of that end as GND). The signal S
7
is fed to the duty-ratio detecting circuit
2
to be converted into the signal S
8
. The signal S
8
is then converted into a control signal S
9
which is a smooth voltage signal, by the capacitor C
2
in the duty-ratio correction filter
3
. The control signal S
9
is fed back to the level shifting circuit LS
1
, by which the amount of level shift is controlled to correct the duty ratio to 1:1.
As described so far, this circuitry comprises two feedback mechanisms, including a loop in the PLL circuit PLL
1
for controlling the phase and the period and a loop in the duty-ratio correction circuit DRC
3
for controlling the duty ratio to be 1:1.
In the circuitry, however, either of the two feedback mechanisms for the feedback clock signal S
2
is likely to interfere with the other. Thus, it may take more time to stabilize the circuitry as compared with a case where the PLL circuit PLL
1
and the duty-ratio correction circuit DRC
3
are separated to operate independently.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a duty-ratio correction circuit comprising: an inverter with an input end receiving a clock, an output end, a first power supply end, a second power supply end, a first current source connected to the first power supply end, and a second current source connected to the second power supply end; and a comparator for comparing a potential of the output end of the inverter with a reference value to output a two-state output signal for controlling a driving force of either the first current source or the second current source.
According to a second aspect of the present invention, the duty-ratio correction circuit of the first aspect further comprises: a control signal generation circuit for generating a control signal by smoothing a variation in the output signal. The control signal controls the amount of current supplied through either of the first current source or the second current source.
According to a third aspect of the present invention, in the duty-ratio correction circuit of the second aspect, the inverter includes a plurality of inverters connected in series; and the inverter having the first current source with a variable driving force and the inverter having the second current source with a variable driving force are alternately placed.
A fourth aspect of the present invention is directed to a clock generation circuit for generating an output clock taking on first and second logical values in synchronization with a reference clock taking on the first and the second logical values. The clock generation circuit comprises: an intermediate clock generation portion for generating an intermediate clock taking on the first and the second logical values on the basis of a comparison between the reference clock and the output clock concerning a first transition from the first logical value to the second logical value; and an output clock generation portion for outputting the output clock by producing a controllable delay in a second transition from the second logical value to the first logical value of the intermediate clock.
According to a fifth aspect of the present invention, in the clock generation circuit of the fourth aspect, the output clock generation portion includes: a transition delay control circuit for generating the output clock by delaying the second transition of the intermediate clock on the basis of a control signal; and a control signal generation circuit for generating the control signal on the basis of a duty ratio of the output clock.
According to a sixth aspect of the present invention, in the clock generation circuit of the fifth aspect, the transition delay control circuit includes: an inverter with an

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