Duty cycle stabilizer

Details Duty cycle stabilizer Duty cycle stabilizer

2007-04-24

2008-10-07

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S172000

Reexamination Certificate

active

07432752

ABSTRACT:
A duty cycle stabilizer circuit (50) receiving an input clock signal and generating an output clock signal having a first duty cycle includes a leading edge pulse generator (52) and a pulse width extender circuit (54). The pulse generator generates a first clock pulse (V1) having a leading edge triggered by the leading edge of the input clock signal and a first pulse width. The pulse width extender circuit generates a second clock pulse (V2) having a leading edge triggered by the leading edge of the first clock pulse and a pulse width being stretched to the desired duty cycle. The duty cycle stabilizer further includes a buffer (64) providing the output clock signal having the first duty cycle, a charge pump (56) receiving the output clock signal directly and a differential amplifier (62) generating an output signal for controlling the pulse width of the first and second clock pulses.

REFERENCES:
patent: 5963071 (1999-10-01), Dowlatabadi
patent: 6426660 (2002-07-01), Ho et al.
patent: 6448828 (2002-09-01), Stark et al.
patent: 6525581 (2003-02-01), Choi
patent: 6943604 (2005-09-01), Minzoni
patent: 6977536 (2005-12-01), Chin-Chieh et al.
patent: 2003/0201806 (2003-10-01), Cho
patent: 2007/0013423 (2007-01-01), Lee

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