Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
1999-10-29
2001-11-20
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S176000, C327S153000, C327S299000, C365S233500
Reexamination Certificate
active
06320437
ABSTRACT:
FIELD OF INVENTION
The invention relates to the regulation of a clock duty cycle for use in conjunction with Very Large Scale Integration (VLSI) microelectronic circuits.
BACKGROUND OF THE INVENTION
In the field of VLSI microelectronic circuits, many digital systems require a certain clock duty cycle (i.e. 50/50%, 40/60%) for proper operation. However, such clock duty cycles are not always readily available. A clock with an inappropriate duty cycle may cause the digital system to fail or force the system to run at a lower clock speed. Although many digital systems desire a 50/50% duty cycle, not all digital systems necessarily desire the same clock duty cycle. Depending on the source of the clock, the duty cycle may not always be known or predictable. Hence, duty cycle correction is needed.
One such approach to duty cycle correction is to use a phase-locked loop to synthesize a clock at double the input frequency, and then to divide down by two to obtain a 50/50% duty cycle. This approach requires the building of a phase-locked loop, which is complex in design, large in area, and high in power. This approach also only limits the output duty cycle to 50/50%.
In U.S. Pat. No. 5,317,202, Waizman discloses a 50% duty-cycle clock generator, which is limited to generating only a 50% duty cycle and its implementation complicated.
In U.S. Pat. No. 5,572,158, Lee et al describe an amplifier circuit with active duty cycle correction to produce a predetermined duty cycle. However, such a circuit uses three operational amplifiers, thus being relatively high in power consumption and large in area.
In U.S. Pat. No. 5,757,218, Blum describes a circuit and a method for signal duty cycle correction, which involves the use of a ring oscillator counter to produce adjustable delays. In order for this approach to have sufficient duty cycle resolution, the ring oscillator must operate at a frequency much higher than the input clock, meaning a large use of power. Lower operating speeds would mean degradation in the duty cycle resolution.
In U.S. Pat. No. 5,550,499, Eitrheim describes an adjustable duty cycle clock generator using multiplexers to adjust the delay in a delay line. The problem with this approach is that the amount of delay needed is not known by the circuit and must be determined elsewhere either through measurement or other dynamic means. This circuit cannot self-correct for the appropriate duty cycle.
In U.S. Pat. No. 5,617,563, Banerjee et al describe a duty-cycle independent tunable clock that uses an adjustable delay line in conjunction with a flip-flop. However, the described circuit is limited by using a fixed delay, once adjusted (by blowing out fuses through a laser), thereby providing a duty cycle for a given adjustment which directly depends on the clock input. Furthermore, the use of blowing out fuses for changing the duty cycle is relatively expensive and demands a larger overall circuit. Once the fuses are set to provide a desired duty cycle for a particular clock frequency, they cannot be changed again to operate with a different frequency or to obtain a different duty cycle.
In U.S. Pat. No. 5,477,180, Chen describes a circuit and a method for generating a clock signal wherein the duty cycle is adjusted independent of the input clock frequency by adjusting a bias voltage at the driver circuit of the output clock, which is driven by the input clock. This bias voltage is generated by a differential amplifier driven by two voltage-adjusted inputs using two adjustable tapped resistors. In Chen's approach, however, at least one operational amplifier and four resistors are required resulting in a relatively large circuit area and high power. Furthermore, the resulting output clock signal is shaped by an RC time constant giving relatively long rise/fall times, especially when duty cycles far beyond 50/50% are desired. Chen teaches that for duty cycles far beyond 50/50%, a few of the described circuits can be cascaded for better rise/fall times. This would require more operational amplifiers and more resistors, hence larger circuit size and greater power consumption. Moreover, there is no provision in Chen's approach for adjusting the duty cycles ‘on the fly’, i.e. whenever desired by the user.
In view of the limitations of the prior art reviewed above, it would be desirable to provide all economical circuit and method for regulating a steady state clock duty cycle over a relatively wide range of selectable duty cycles, without being dependent on an actual input clock frequency value.
SUMMARY OF THE INVENTION
An object of this invention is to provide an improved duty cycle regulator that can receive an input clock signal within a certain range of frequencies having any arbitrary duty cycle and to output a clock signal having a pre-selected duty cycle at the same frequency as that of the input clock.
It is another object of the present invention to allow a selection, within limits, of the output clock's duty cycle for a given range of operating frequencies, where such selection can be optionally made as a programmable feature where the duty cycle generated may be changed ‘on the fly’.
In accordance with an aspect of the present invention, there is provided a duty cycle regulator for receiving an input clock signal having an input clock period, and an arbitrary input duty cycle, and for deriving from the input clock signal, an output clock signal having a pre-selected duty cycle and the same period as the input clock period. The duty cycle regulator includes: clock output means for providing an output clock signal, which periodically alternate between a first signal level and a second signal level; and delay means responsive to the output clock signal, for providing a delayed signal to the clock output means, following a transition in the output clock signal from the first level to the second level, after a pre-selected fraction of the input clock period.
In an embodiment of the present invention, the clock output means is switchable between a first and a second state providing the first and second signal levels respectively. When a transition between low and high levels occurs in the input clock signal along a pre-determined direction, the clock output means responds by attaining the first state thereby giving the first output clock level, and thereafter switches to the second state thereby giving the second output clock level upon termination of the pre-selected fraction of the input clock period.
In a hardware implementation of the present invention, the clock output means can be in the form of a bistable circuit such as a reset/set flip-flop circuit switchable between a first and a second state. In such an implementation the bistable circuit has a first input port for receiving an input clock pulse, a second bistable input port and an output clock port for providing said output clock signal. The delay means has an input port coupled to the output clock port, and an output port coupled to the second bistable input port for providing a delayed signal after a pre-selected fraction of the input clock period, following a switching of the bistable circuit from the second state to the first state. When, in this configuration, an input clock pulse is provided to the first bistable input port, the bistable circuit switches to said first state giving a first output clock level, and thereafter the delay circuit provides the delayed pulse to the second bistable input port, thereby switching the bistable circuit to the second state and giving a second output clock level.
Conveniently the input clock pulse can be derived from the input clock signal by a clock pulse generator comprising means for deriving from the input clock signal a first clock signal, followed by a second clock signal delayed from the first clock signal. Here the input clock pulse is generated when the first clock signal overlaps with the second clock signal.
The pulse generator means can be configured to comprise: at least one first delay inverter having a first input port adapted to receive the input cl
Mosaid Technologies Inc.
Nguyen Minh
Price Heneveld Cooper DeWitt & Litton
Wells Kenneth B.
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