Duty cycle optimized prescaler

Details Duty cycle optimized prescaler Duty cycle optimized prescaler

1999-12-03

2001-07-31

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S299000

Reexamination Certificate

active

06268751

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to duty cycle clocks, and more particularly to a duty cycle optimized prescaler used in integrated circuits to optimize the duty cycle of a clock to fifty percent.
BACKGROUND OF THE INVENTION
Prescaler circuits generate an output signal that is a fractional scale factor related to the input signal. The output signal is synchronous and proportional in frequency to a clock signal. Some circuits provide an unbalanced duty cycle which is at a fixed rate. A clock signal output of a duty cycle unbalanced prescaler is fixed, for example, to:
(1). 1 cycles low and N/2 cycles high, when the prescaler value N is an even number and 1<N>15.
(2). 1.5 cycle low and N/2-1.5 cycles high, when prescaler value N is an odd number and
2
<N<16.
(3). 4 cycle low and N/2-4 cycles high, when prescaler value N is an even number and 15>N>63.
(4). 4.5 cycle low and N/2-4.5 cycles high, when prescaler value is an odd number and 16<N<64.
This scheme results in a duty cycle unbalanced clock. This causes problems in high frequency designs because of the narrow clock pulse. This design is technology dependent.
Alternate solutions have been used using digital phase lock loop (DPLL) which can yield a 50% duty cycle most of the time. The main draw-back is that this approach requires more silicon space on an integrated circuit chip, and thus more power.
A 50% duty cycle divide-by-N counter is described in U.S. Pat. No. 5,127,036. The described circuit generates a duty cycle output clock signal having a fifty percent duty cycle.
U.S. Pat. No. 5,491,440, describes a circuit for automatically adjusting the duty cycle of an output clock. The circuit utilizes a D-type flip-flop and requires an input of a referenced voltage, a reset signal, and input clock signal.
SUMMARY OF THE INVENTION
The invention is a logic synthesizable RTL implementation of a programable baud rate generator used in integrated circuits. The invention can be implemented in hardware description language (HDL) such as verilog or VHDL and then synthesized using actual gate implementation. This allows the invention to be portable from one design to another design that is technology independent.
The invention solves the problem of an unbalanced duty cycle clock used in an integrated circuit. In order to prevent this unbalance, the present invention optimizes the clock duty cycle as close as possible to fifty percent. This is achieved by employing two counters: one to count negative edges of the clock pulse, and one to count positive edges of the clock pulse. Each counter output is connected to a comparator which compares each counter output to a prescaler setting. The comparator outputs are input to an OR gate, the output of which, when a logic 1, resets the counters and toggles a flip-flop circuit providing a clock output signal.


REFERENCES:
patent: 5250939 (1993-10-01), Takanashi et al.
patent: 5963885 (1999-10-01), Macq

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