Patent
1980-08-25
1982-12-21
Heyman, John S.
328 48, 328 61, H03K 505, H03K 708
Patent
active
043652026
ABSTRACT:
A digitized duty cycle pulse generator capable of resolution finer than the period of the available source clock signal. The invention comprises a means for generating a clock pulse signal having a repetition of f.sub.c, counter means responsive to said clock pulse signal to cycle iteratively through a count of n, and storage means for storing a variable binary value m, where m<n and m is the length of the desired duty cycle pulse, and where m
is the duty cycle. Also provided are logic means comprising comparator means responsive to the instantaneous count l in said counter means and the value m in said storage means when m is not an integer to produce a first logic level signal when l<m and a second logic level signal when l>m during first selected cycles of said counter means through said count of n, and to produce said first logic level signal when l<(m+1) and said second logic level signal when l>(m+1) and during second selected cycles of said counter means through said count of n.
REFERENCES:
patent: 3614632 (1971-10-01), Leibowitz et al.
patent: 3629710 (1971-12-01), Durland
patent: 3836858 (1974-09-01), Kitano
patent: 3958182 (1976-05-01), Sauthier
patent: 4141376 (1979-02-01), Frey
patent: 4166247 (1979-08-01), Miyazawa
patent: 4236114 (1980-11-01), Sasaki
Cohen Samuel
Heyman John S.
Phillion Donald W.
RCA Corporation
Tripoli Joseph S.
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