Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2001-04-02
2002-09-24
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S036000, C327S037000, C377S016000
Reexamination Certificate
active
06456134
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a duty cycle discriminating circuit, and more particularly to a duty cycle discriminating circuit which is used, for example, in a video tape recorder and the like and in which a threshold point of duty cycle discrimination can be varied.
BACKGROUND OF THE INVENTION
A duty cycle discriminating circuit or a pulse width discriminating circuit is used, for example, in a video tape recorder (VTR), such as a VHS type VTR, and the like. The duty cycle discriminating circuit is used for determining whether a duty cycle of an input pulse signal is larger or smaller than a threshold value.
As one of conventional duty cycle discriminating circuits, there is known a discriminating circuit used in a VISS detecting circuit which is integrated in &mgr;PD78492x series IC devices manufactured by NEC Corporation.
The VISS is an abbreviation of VHS Index Search System and is used, for example, for detecting or indexing a start portion of a playback video signal. In the VISS detecting circuit, a duty cycle discriminating circuit is used to detect a predetermined binary pattern, that is, a VISS pattern corresponding an index signal. The predetermined binary pattern is represented by using binary “1” and “0” corresponding to different duty cycles of a control signal recorded, for example, on a VHS video tape.
FIG. 10
is a block diagram showing a conventional duty cycle discriminating circuit used in the VISS detecting circuit.
FIG. 11
is a timing diagram showing an operation of the duty cycle discriminating circuit of FIG.
10
. The duty cycle discriminating circuit of
FIG. 10
comprises an up/down counter with sign bit or a signed up/down counter
51
, a preset value register
52
, an edge detecting circuit
55
, a control register
56
, and a latch circuit
58
.
The up/down counter
51
receives a count clock signal FCLK having a fixed frequency. The up/down counter
51
also receives a playback control signal (PBCTL signal), and performs a count up operation or a count down operation depending on the potential level of the PBCTL signal. For example, when the PBCTL signal is “0”, the up/down counter
51
performs a count down operation, and when the PBCTL signal is “1”, the up/down counter
51
performs a count up operation. An enable/clear of the up/down counter
51
is controlled by a signal from the control register
56
.
The preset value register
52
stores a data value to be written into the up/down counter
51
. The data value is outputted from the preset value register
52
in synchronization with a falling edge of a re-load signal supplied from the edge detecting circuit
55
.
The most significant bit (MSB) of the up/down counter
51
is a sign bit. When the sign bit is “0”, the up/down counter
51
shows a positive number, and when the sign bit is “1”, the up/down counter
51
shows a negative number. This most significant bit (MSB) is inputted to the latch circuit
58
. The latch circuit
58
may be a D-type flip-flop circuit, and holds the MSB of the up/down counter
51
in response to a rising edge of the re-load signal outputted from the edge detecting circuit
55
. The MSB held by the latch circuit
58
becomes an output signal, that is, a discrimination result signal, of the duty cycle discriminating circuit.
The edge detecting circuit
55
outputs a re-load signal when it detects an edge designated by the content of the control resistor
56
.
It is possible to write data into the control register
56
and into the preset value register
52
from a central processing unit (CPU) and the like which is disposed outside of this pulse width discriminating circuit and which is not shown in the drawing.
With reference to
FIGS. 11A-11C
, an operation of the conventional duty cycle discriminating circuit of
FIG. 10
will be described briefly. As shown in the timing diagrams of
FIGS. 11A-11C
, the conventional duty cycle discriminating circuit of
FIG. 10
discriminates duty cycles by using the up/down counter
51
with a sign bit or a signed up/down counter
51
. The up/down counter
51
counts up the count clock signal FCLK during a period in which the PBCTL signal is in a high potential level, and counts down the count clock signal FCLK during a period in which the PBCTL signal is in a low potential level.
Usually, in order to reduce an error of discrimination, when the duty cycle of the PBCTL signal is to be discriminated, a middle value between the possible duty cycles is previously stored in the preset value register
52
.
That is, in the VISS detection, the PBCTL signal has a duty cycle of 60% and a duty cycle of 30% (correctly, 27.5%), corresponding, for example, to “0” and “1” for representing binary data. Therefore, discrimination between these two kinds of duty cycles is performed by using a duty cycle of approximately 45%, which is a middle value between 60% and 30%, as a threshold point.
In order for the up/down counter
51
to become zero after one period of the PBCTL signal when the PBCTL signal having a duty cycle of 45% is inputted into the up/down counter
51
, it is necessary to store a count value corresponding to 10% of one period of the PBCTL signal into the preset value register
52
. As an example, when one period of the PBCTL signal corresponds to 200 clock pulses, it is necessary to store data “20” into the present value register
52
.
In this structure, when the duty cycle of the PBCTL signal is larger than 45%, for example, 60%, the count value of the up/down counter
51
with sign bit becomes a positive value, and when the duty cycle of the PBCTL signal is smaller than 45%, for example, 30%, the count value of the up/down counter
51
with sign bit becomes a negative value. Thereby, it is possible to discriminate the duty cycle of the PBCTL signal.
As a second prior art technology for duty cycle discrimination, the following method is known which is not shown in the drawing.
That is, in this method, a counter and two registers A and B are used. The counter receives and counts up a clock pulse signal having a constant period. The registers A and B store count values of the counter during particular times specified by a signal to be measured or discriminated. The register A stores a count value corresponding to a time during which the signal to be measured is in a high potential level, and the register B stores a count value corresponding to one period of the signal to be measured.
The duty cycle of the signal to be measured is obtained by performing an arithmetic operation on the values stored in the registers A and B by an external CPU.
That is, the duty cycle is obtained by the following arithmetic operation.
Duty cycle=(count value of register A)/(count value of register B)
This method is very simple, and provides a precise duty cycle value.
As a third prior art technology, there is known a duty cycle discriminating circuit in which a period of a count clock signal is selected depending on a period of an input signal, that is, a count value of the input signal. Thereby, even if a period of the input signal varies over a wide range, it is possible to discriminate a duty cycle by using a constant re-load value.
However, with respect to the first prior art method, when a videotape is wound forward (fast-forward) or rewound in a video tape recorder (VTR), the period of the PBCTL signal varies depending on variations in motor speed. Even in such case, it is necessary to correctly discriminate the duty cycle of the PBCTL signal. In this case, in order to detect whether the PBCTL signal shows the VISS pattern or not, it is only necessary to discriminate the duty cycle between two kinds of duty cycles, that is, between 30% and 60%.
In the timing diagram of
FIG. 11
, the initial re-load value of the up/down counter
51
is 00H, that is, zero in hexadecimal notation. However, usually, when the duty cycle discrimination is to be performed, a middle value between the two kinds of duty cycles is previously stored in the preset value register
52
, and the middle value stored in the preset va
Callahan Timothy P.
NEC Corporation
Nguyen Minh
Whitham Curtis & Christofferson, P.C.
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