Duty cycle correction using input clock and feedback clock...

Details Duty cycle correction using input clock and feedback clock... Duty cycle correction using input clock and feedback clock...

2008-05-20

2008-05-20

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000, C327S175000, C327S176000

Reexamination Certificate

active

11308568

ABSTRACT:
A clock generator corrects the duty cycle of an input clock. The input clock has a poor duty cycle such as less than 50%. The input clock is applied to a phase detector of a phase-locked loop (PLL). A voltage-controlled oscillator (VCO) of the PLL drives a feedback clock that is also applied to the phase detector. An edge-triggered set-reset SR flip-flop generates a duty-cycle-corrected output clock. The SR flip-flop is set by the leading edge of the input clock, but is reset by the trailing edge of the feedback clock. The VCO generates the feedback clock with the desired duty cycle, such as 50%. The leading edge of the output clock is generated by the input clock, avoiding noise generated by the PLL, while the trailing edge of the output clock is generated by the feedback clock and has PLL noise, but corrects for the desired duty cycle.

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