Duty cycle correction of a multi-gigahertz clock signal with...

Pulse or digital communications – Receivers – Angle modulation

Reexamination Certificate

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Details

C327S172000, C327S175000, C327S122000, C700S028000, C331S048000, C330S010000

Reexamination Certificate

active

07496155

ABSTRACT:
A clock recovery circuit includes a crossover adjustment circuit operable to adjust a crossover point to adjust a corresponding duty cycle. The adjustment circuit comprises a feedback adjustment combining element which is implemented as summing elements and a crossover point control clock amplifier, an operational amplifier with a resistor in place of a low pass filter at an input of the operational amplifier and feedback driver. The summing element within the feedback adjustment combining element combines input clocks with feedback signals, the crossover point control clock amplifier includes adjustment driver, the two cross coupled PMOS along with the resistor connected between them, reshape input clocks, adjust cross over point and provide output clocks with DCD corrected. A modified Miller capacitor comprising a resistor in series with a capacitor across a drain and gate of a cascode transistor pair is utilized in an output stage to adjust corner frequencies.

REFERENCES:
patent: 4959557 (1990-09-01), Miller
patent: 5280424 (1994-01-01), Rony et al.
patent: 6016081 (2000-01-01), O'Shaughnessy
patent: 6084452 (2000-07-01), Drost et al.
patent: 6356129 (2002-03-01), O'Brien et al.
patent: 6492868 (2002-12-01), Kirn
patent: 6593789 (2003-07-01), Atallah et al.
patent: 6611218 (2003-08-01), Lu et al.
patent: 6864728 (2005-03-01), Lu

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