Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2000-08-17
2001-11-20
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S037000, C327S165000, C327S285000
Reexamination Certificate
active
06320438
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to clock generators, and more particularly to clock duty-cycle correction circuits.
BACKGROUND OF THE INVENTION
Many complex electronic systems rely on synchronous or clocked digital circuits. For example, a microprocessor or central processing unit (CPU) often has a clock input that controls the timing of operations such as instruction decode and memory access. To ensure reliable operation, the microprocessor may have very strict input requirements for this clock input, such as frequency, voltage levels, and duty cycle.
As system designers compete with one another for the fastest-performing chips, they often squeeze internal delays and resort to design tricks that use both rising and falling edges of the clock. The clock's duty cycle then becomes more critical, since variations in duty cycle reduce available setup times to either the rising or falling edges of the clock. Thus a tendency for tighter duty-cycle requirements has occurred in highly competitive markets.
Clocks are generally produced by a crystal oscillator and passed through a driver before being input to a microprocessor or other very-large-scale-integration (VLSI) chip. System designers can use special clock drivers that adjust the clock's characteristics.
Many duty-cycle correctors use threshold-level compensation. The threshold level is adjusted to adjust the duty cycle. See U.S. Pat. No. 4,959,557 by Miller which uses a feedback loop to adjust the threshold of the input to buffer
48
. These threshold-adjustment correctors are limited since adjusting the threshold voltage provides only a small change in duty cycle when a clock with sharp edges (high slew rate) is used. Large duty cycle adjustments, such as from 80%-20% to 50%—50% are not feasible unless perhaps a very slow-slewing clock is used.
Other clock drivers use slew-time compensation to adjust duty cycle over a wide range. A slow-slewing clock signal is modulated in a modulator. The modulator is a complementary metal-oxide-semiconductor (CMOS) inverter with additional transistors in series to power and ground. The additional series transistors have gates connected to a control voltage of about Vcc/2. The control voltage is adjusted slightly to limit current through the series transistors, adjusting a ratio of up and down source currents. This changes the up and down slew rates of the clock. The slow-slewing clock output by the modulator is then cleaned up to a high-slew-rate clock by a driver stage.
For example, U.S. Pat. No. 5,477,180 by Chen uses a CMOS modulator
16
that adjusts up and down source currents. A feedback loop from the modulator output is used to generate a control or bias voltage that controls the up and down source currents in the modulator. While such a circuit is useful, mismatch of R
3
and R
4
resistor values in the feedback loop can introduce duty-cycle detector sensing error. Further inaccuracies may occur since the modulator outputs a slow-slew clock that may need a further driver stage to sharpen the edges to a higher slew rate.
Since Chen's feedback loop senses the output from the modulator rather than the output from a later driver stage, the slow-slew clock is sensed by the feedback loop. Sensing a slow-slew clock rather than a high-slew clock is undesirable since errors can be increased and clock stability diminished. A more linear and stable duty-cycle corrector is desired.
Another duty-cycle adjustor is described in U.S. Pat. No. 5,907,254 by Chang. Two differential amps are used in his feedback loop(s). Both threshold and slew-time compensation are used in this complex feedback. While useful, a more accurate and linear duty-cycle correction circuit is desired that uses a single feedback loop. It is desired that the feedback loop senses the duty cycle of the actual clock driven to the microprocessor, not the slow-slew-rate clock output from the modulator. More accurate filtering of the duty cycle is desired that does not introduce distortions due to resistor mismatch within the filter. A smoothed control voltage is desired for controlling the source currents in the modulator to further reduce distortions and ensure clock stability.
SUMMARY OF THE INVENTION
A duty-cycle-correcting clock driver has a clock input that receives an input clock with an input duty cycle that varies from a target duty cycle. A modulator receives the input clock and generates an intermediate clock. It adjusts rise and fall delays of the intermediate clock in response to a control signal to adjust the input duty cycle. A driver receives the intermediate clock. It generates a final clock that is corrected to the target duty cycle by the modulator.
A feedback loop generates the control signal to the modulator. It receives the final clock. The feedback loop includes an error amplifier that amplifies a difference between a first input and a reference voltage applied to a second input to generate an amp output. A detector filter has a series resistor between the final clock and the first input of the error amplifier. The detector filter also has an input capacitor attached to the first input. An output capacitor is coupled to the amp output. It filters the amp output to generate the control signal to the modulator. Thus the feedback loop includes the series resistor and senses the final clock to generate the control signal for the modulator.
In further aspects of the invention the modulator has a source-limiting p-channel transistor having a gate coupled to the control signal and a source connected to a power supply, for limiting charging current in response to the control signal. A switching p-channel transistor is coupled to receive charging current from the source-limiting p-channel transistor. It has a gate coupled to the input clock and a drain driving the intermediate clock. A source-limiting n-channel transistor has a gate coupled to the control signal and a source connected to a ground supply. It limits discharging current in response to the control signal. A switching n-channel transistor is coupled to sink discharging current to the source-limiting n-channel transistor. It has a gate coupled to the input clock and a drain driving the intermediate clock.
In still further aspects the source-limiting p-channel transistor and the source-limiting n-channel transistor operate in a linear region.
In other aspects the control signal is a voltage of about Vcc/2 when the input duty cycle is 50%, but above Vcc/2 when the input duty cycle is above 50% and below Vcc/2 when the input duty cycle is below 50%. Thus the control signal varies in response to the input duty cycle.
In further aspects of the invention, the intermediate clock generated by the modulator has a slower slew rate than the final clock generated by the driver. Thus the driver improves slew rate.
In still further aspects a threshold gate is coupled to the final clock from the driver. It drives the series resistor in the detector filter with a modified signal derived from the final clock. The modified signal has transitions when the final clock crosses a measured threshold. The measures threshold is a switching threshold of the threshold gate. Thus the measured threshold determines threshold measurement of the final clock while the reference voltage determines when the control signal is adjusted.
REFERENCES:
patent: 4408168 (1983-10-01), Higuchi
patent: 4527075 (1985-07-01), Zbinden
patent: 4736118 (1988-04-01), Fischer
patent: 4926178 (1990-05-01), Mallinson
patent: 4959557 (1990-09-01), Miller
patent: 5208595 (1993-05-01), Engel et al.
patent: 5231320 (1993-07-01), Kase
patent: 5477180 (1995-12-01), Chen
patent: 5614855 (1997-03-01), Lee et al.
patent: 5835041 (1998-11-01), Zydek et al.
patent: 5856753 (1999-01-01), Xu et al.
patent: 5869992 (1999-02-01), Sekino
patent: 5907254 (1999-05-01), Chang
patent: 5920217 (1999-07-01), Mellot
patent: 6028491 (2000-02-01), Stanchak et al.
Auvinen Stuart T.
Callahan Timothy P.
Nguyen Minh
Pericom Semiconductor Corp.
LandOfFree
Duty-cycle correction driver with dual-filter feedback loop does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Duty-cycle correction driver with dual-filter feedback loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Duty-cycle correction driver with dual-filter feedback loop will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2579165