Duty cycle correction circuit of delay locked loop

Details Duty cycle correction circuit of delay locked loop Duty cycle correction circuit of delay locked loop

2000-06-29

2002-01-29

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S158000, C327S544000

Reexamination Certificate

active

06342801

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a duty cycle correction circuit of a delay locked loop in a Rambus dynamic random access memory (DRAM), and more particularly to a duty cycle correction circuit in a delay locked loop for reducing the refresh time by compulsorily correcting the capacitance of a storage capacitor lost in transition from a power save mode to a normal mode to a predetermined value.
2. Description of the Related Art
In general, a Rambus DRAM is a packet driving type memory device which transfer data and control signals with a packet. A Rambus controller controls Plural Rambus DRAMs through a Rambus channel and plural Rambus DRAMs are connected to a Rambus channel. A Rambus interface is constituted in the respective Rambus DRAM, respectively so as to transfer data through the Rambus channel between them. Because the plural Rambus DRAMs coupled to the Rambus channel is controlled by one controller, the respective Rambus DRAMs have different phase differences so as to recognize the data and the control signals from the controller at the same time. That is, in case of the Rambus DRAM which is far separated from the controller, it makes the data to be processed fast and in case of the Rambus DRAM which is near the controller, it makes the data to be processed slowly.
Generally, the Rambus DRAM includes a normal mode and a power save mode, wherein the power save mode includes a nap mode and a power down mode.
FIG. 1
shows a circuit of a Rambus DRAM having a power save mode in the prior art. The Rambus DRAM having the power save mode includes a packet controller
200
for analyzing a control packet signal Ctrl_PKT from an external channel to generate a control signal Cntrl for controlling a power mode operation and an operation code signal op_code for determining an operation mode.
The Rambus DRAM includes a power mode controller
300
which generates a nap mode signal Nap and a power down mode signal PDN and a self refresh enable signal Self_Refresh_en by the control signal Cntrl from the packet controller
200
. The Rambus DRAM includes a delay locked loop circuit
400
which receives the power down mode signal PDN and the nap mode signal Nap and an external clock signal CLK_in to generate an internal clock signal CLK_out and a memory core
100
having a refresh counter controlled by the self refresh enable signal Self_refresh_en.
The packet controller
200
receives the packet control signal Ctrl_PKT from an external channel outside the Rambus DRAM and generates the control signal Cntrl and the operation code signal op_code. The control signal Cntrl is a signal for controlling whether the Rambus DRAM operates with the power save mode, or not and the operation code signal op_code is a signal of 2 bits for determining the respective operation modes. For example, in case of the operation code signal op_code of 2 bits, the op_code of “00” forbids the Rambus DRAM to be changed into the power save mode, and the op_code of “01” changes it to a power down mode, and the op_code of “10” changes it to a nap mode Nap and the op_code of “11” changes it to a doze mode.
The power mode controller
300
receives the operation code signal op_code and the control signal Cntrl from the packet controller
200
to generate the self refresh enable signal Self_Refresh_en to the memory core
100
and the nap mode signals Nap and the power down mode signals PDN to the delay locked loop circuit
400
. The self refresh enable signal Self_fresh_en controls the refresh counter built in the memory core
100
to perform the self refresh operation. The nap mode signal Nap and the power down mode signal PDN control the delay locked loop (DLL) circuit
400
to operate in accordance with the power state.
The delay locked loop circuit
400
receives the clock signal CLK_in received from the exterior of the system and generates the internal clock signal CLK_out required interior the system with synchronization to the phase of the external clock signal CLK_in.
The construction and operation of the delay locked loop circuit
400
will be described with reference to FIG.
2
. The delay locked loop circuit
400
includes a controller
410
, a bias generator
420
, a duty cycle correction circuit
430
, a phase detector and mixer
440
, a clock amplifying part
450
and a clock buffer
460
. The controller
410
controls the bias generator
420
, the duty cycle correction circuit
430
and the phase detector and mixer
440
, the clock amplifying part
450
and the clock buffer
460
by the nap mode signal Nap and the power down mode signal PDN from the power mode controller in FIG.
1
.
The duty cycle correction circuit
430
generates a control signal for controlling a clock pulse width of high or low state to the clock amplifying part
450
by a mode signal from the controller
410
and a bias signal from the bias generator
420
. The clock buffer
460
generates the internal clock signal CLK_OUT having the same phase difference as the external clock signal CLK_IN to an interior of the system.
The phase detector and mixer
440
receives the external clock signal CLK_IN and the final clock signal CLK_OUT from the clock buffer
460
and compares the phases of the clock signals to control the clock amplifying part
450
and the clock buffer
460
to coincide the phase difference between the clock signals.
The clock amplifying part
450
amplifies the clock signal from the phase detector and mixer
440
and provides the amplified signal to the clock buffer
460
. The bias generator
420
provides the bias to the duty cycle correction circuit
430
and the clock buffer
460
by the mode signal from the controller
410
.
FIG. 3
shows the duty cycle correction circuit of the delay locked loop circuit in the prior art. The prior duty cycle correction circuit
430
includes a differential amplifying stage
432
which differential-amplifies two clock signals clki and clkib as input signals to generate output signals through nodes Nd
6
and Nd
7
, when the bias voltage Vbiasn from the bias generator
420
has a high level and the mode signal napb which indicates not the nap mode Nap but the power save mode has a high level.
The prior duty cycle correction circuit
430
further includes a signal transfer switch stage
434
for providing the output signals Nd
6
and Nd
7
from the differential amplifying stage
432
to first and second output terminals dcc and dccb by control signals capon and caponb and a storage capacitor stage
436
for storing the output signals dcc and dccb of the first and second output signals.
First, when the bias voltage Vbiasn from the bias generator
420
has a high level and the mode signal napb indicating the power save mode has a high level, the NMOS transistors N
3
-N
6
, N
9
, N
10
, N
15
and N
16
and the PMOS transistors P
1
-P
3
and P
5
-P
7
are turned on to be ready to the differential amplifying stage
432
to operate. If the input signals clki and clkib are provided to gates of the NMOS transistors N
1
and N
2
, the differential amplifying stage
432
generates the differential-amplified output signals though the node Nd
6
and Nd
7
. If the bias voltage Vbiasn is a high level and the mode signal napb is a high level, when the clock signal clki is a high level and the clock signal clkib is a low level, the output signal of the node Nd
6
becomes a low level and the output signal of the node Nd
7
becomes a high level.
The signal transfer switching stage
434
includes a transfer gate including a PMOS transistor P
9
and a NMOS transistor N
19
for transferring the output signal Nd
6
of the differential amplifying stage
432
as the output signal dccb by the control signals capon and caponb; a transfer gate including a PMOS transistor P
12
and a NMOS transistor N
20
for transferring the output signal Nd
7
of the differential amplifying stage
432
as the output signal dcc by the control signals capon and caponb.
The signal transfer switching means
434
includes a NMOS transistor N
21
for a capacitor connected between the con

Affiliated with

Also associated with

Rating

Duty cycle correction circuit of delay locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Duty cycle correction circuit of delay locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Duty cycle correction circuit of delay locked loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2817316