Duty cycle correction circuit for high-speed clock signals

Details Duty cycle correction circuit for high-speed clock signals Duty cycle correction circuit for high-speed clock signals

2007-12-21

2010-06-08

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S172000, C327S173000

Reexamination Certificate

active

07733143

ABSTRACT:
The present invention implements an apparatus for correcting duty cycle distortion in high speed clock signals. The apparatus includes delay cells that delay each of first and second differential initial clock signals. The apparatus further includes a latch that generates an output clock signal based on the delayed first and second differential initial clock signals. The apparatus further includes a differential feedback buffer that converts the output clock signal into first and second differential feedback signals. The apparatus further includes a feedback circuit that adjusts the delay cells based on the first and second differential feedback signals.

REFERENCES:
patent: 6320437 (2001-11-01), Ma
patent: 6411145 (2002-06-01), Kueng et al.
patent: 6844766 (2005-01-01), Sun
patent: 7282977 (2007-10-01), Lee
patent: 7496155 (2009-02-01), Lu et al.
patent: 2008/0024182 (2008-01-01), Choi et al.

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