Duty-cycle correction circuit

Details Duty-cycle correction circuit Duty-cycle correction circuit

2007-04-10

2007-04-10

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S291000

Reexamination Certificate

active

11129996

ABSTRACT:
A duty-cycle correction (DCC) circuit adapted to adjust the duty cycle of a differential clock signal to conform it to the requirements of a half-rate clocking system. In a representative embodiment, the DCC circuit has a buffer circuit adapted to generate a differential output clock signal by adding offset voltage to a differential input clock signal. A feedback loop coupled to the buffer circuit processes the output clock signal to evaluate deviation of its duty-cycle value from 50% and, based on the evaluation, configures the buffer circuit to adjust the offset voltage such that the duty-cycle deviation is reduced. The feedback loop and the buffer circuit are controlled by a duty-cycle calibration engine, e.g., a digital logic circuit adapted to determine an appropriate value for the offset voltage, which causes the duty-cycle value in the output clock signal to be substantially 50% regardless of the duty-cycle value in the input clock signal. As a result, technological limitations in the circuit-fabrication process do not significantly reduce the yield of chips for half-rate clocking systems.

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“A 1GHz 1.8v Monolithic CMOS PLL With Improved Locking,” by Jian Zhou and Huiting Chen, 0-7803-7150-X, IEEE, 2001, pp. 458-461.
“A 50% Duty-Cycle Correction Circuit For PLL Output,” by Toru Ogawa and Kenji Taniguchi, 0-7803-7448-7/02, IEEE, 2002, pp. VI 21-24.

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