Duty-cycle correction circuit

Details Duty-cycle correction circuit Duty-cycle correction circuit

2003-03-20

2004-07-20

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S161000

Reexamination Certificate

active

06765421

ABSTRACT:

FIELD OF INVENTION
The present invention relates to a method and an apparatus for generating two signals with a pre-determined spacing between mutually corresponding signal edges.
RELATED APPLICATIONS
This application claims the benefit of the Mar. 28, 2002 priority date of German application DE 102.14.304.8-53, the contents of which are herein incorporated by reference.
BACKGROUND
Semiconductor devices, such as, for example, DRAM memory devices or other microelectronic apparatuses, are generally provided with delay locked loops (DLLs) in order to synchronize the data output with an external clock signal, or bring them in phase with one another.
In the so-called double data rate scheme, a data bit is driven with the rising clock edge and a data bit is driven with the falling clock edge. If the duty ratio (duty cycle) is assumed to be 0.5, i.e. the HIGH level of the clock signal has the same length as the LOW level of the clock signal, the maximum bit duration amounts to half of the clock period in the double data rate scheme (DDR). However, the clock typically does not have a precise duty ratio of 50%. If the data are then simply driven by the edges, this leads to a shift in the length of the bit duration, i.e. the period of time in which the data are valid.
In order to improve the uniformity of the bit duration, duty ratio correction circuits have been proposed in the past. The aim of a duty ratio correction circuit is to provide a clock on a chip with a duty ratio of 0.5 even if an imprecise external clock signal having a duty ratio that deviates from this is present. However, the previously known methods are difficult to implement and consume a large amount of current, such as e.g. in a DLL with a differential current mode in which the crossover point of the internal clocks is shifted by adding an analog current onto for example the true, but not the complementary, clock path.
An architecture that is already used in delay locked loops (DLLs) has two delay lines in order to eliminate the sensitivity to propagation delay differences between the rising and falling clock edges.
FIG. 5
illustrates such an architecture having two delay devices
5
(delay lines). Two receivers
22
A,
22
B, which are connected in a complementary manner to a true clock signal
1
and a complementary clock signal
2
, are provided in this arrangement. The receivers generate a clock signal
3
and a clock signal
4
complementary thereto, which run through identically controlled delay devices
5
(delay lines). After passing though a driver stage
23
, a delayed internal clock signal
11
and an inverted delayed clock signal
12
are present. The delayed internal clock signal
11
is fed via a feedback
8
, which inevitably has a certain delay (feedback delay), in the form of a delayed signal
21
to a phase detector
7
, which compares the phase of the delayed signal
21
with the phase of the clock signal
3
and accordingly forwards a control signal
17
(FASTER) or a control signal
18
(bSLOWER) to a conventional pump device
6
(charge pump). A control signal
19
,
20
is provided in the pump device
6
(charge pump), by means of which control signal the two delay devices
5
(delay lines) are controlled virtually in parallel.
FIG. 6
shows part of a conventional pump device
6
(charge pump) in a diagrammatic illustration, in which the control signal
17
(FASTER) serves to drive an n-channel field-effect transistor
25
, the control signal
18
(bSLOWER) driving a p-channel field-effect transistor
24
. A control signal
20
, e.g. a voltage level, is realized by charging or discharging a capacitor
28
by means of the switching devices
24
,
25
, which, according to the control signals
17
,
18
, connects a voltage source
27
or ground
26
to one terminal of the capacitor
28
, while the supply voltage
27
is applied to the other terminal.
FIG. 7
shows a current mirror, which is likewise part of the conventional pump device
6
(charge pump) for generating a control signal
19
from the control signal
20
. To that end, the control signal
20
is fed to the drive terminal of a p-channel field-effect transistor
24
, which can connect a supply voltage source
27
to one terminal of a capacitor
28
for the purpose of charging that capacitor
28
, the other terminal of the capacitor
28
being connected to ground
26
. The voltage across the capacitor corresponds to the control signal
19
, which is fed to the drive terminal of an n-channel field-effect transistor
25
in order to be able to discharge the capacitor
28
.
FIG. 8
represents the diagrammatic illustration of a delay device
5
(delay line), in which an input signal
29
is fed in parallel to a p-channel field-effect transistor
24
and to an n-channel field-effect transistor
25
. The forwarding of the signal
29
is both dependent on the control signal
20
, which is fed to the drive terminal of a p-channel field-effect transistor
24
, and on a signal
19
, which is fed to an n-channel field-effect transistor
25
. A supply voltage
27
can be forwarded via the p-channel field-effect transistors
24
according to the input signal
29
and the control signal
20
, whereas the potential of the ground terminal
26
can be forwarded via the n-channel field-effect transistors
25
according to the input signal
29
and the control signal
19
. This forwarded signal is again fed to a stage of essentially identical construction, which generates the output signal
30
of the controllable delay device
5
(delay line). The input signal
29
is delayed or extended by a specific period of time depending on the control signals
19
,
20
and controllable edges are thus generated in the output signal
30
in a controlled fashion.
FIG. 9
shows the signal profiles of a delay locked loop according to
FIG. 5
with a dual delay device
5
(dual delay line). The external clock signal
1
has a shifted duty ratio (duty cycle) since the HIGH level of the clock signal is present for a different length of time than the LOW level of the clock signal. The complementary external clock signal
2
corresponds to the inverted external clock signal
1
. In comparison with the external clock signal
1
, a clock signal
3
, which is generated on the chip and has to pass through the receiver
22
a
, is slightly delayed, which equally applies to the complementary clock signal
4
generated on a chip. In the locked state illustrated, the signal
21
delayed via the feedback
8
has no phase difference with respect to the clock signal
3
generated on the chip. The shift between the delayed signal
21
of the feedback and the delayed internal clock signal
11
results from the feedback delay, the shifted delayed clock signal
12
in this case having an inverted profile with respect to the delayed internal clock signal
11
.
Consequently, with an apparatus according to
FIG. 5
, although a delayed internal clock signal
11
and a clock signal
12
complementary thereto can be generated with precisely corresponding edge instants, no correction of the duty ratio (duty cycle) can be performed if the duty ratio of the external clock signal
1
deviates from the desired value of 0.5.
The control signal of the delay device
5
(delay line) is generated in a conventional manner by locking the phase of the delayed internal clock signal
11
with the received clock signal
3
and the use of a pump device
6
in accordance with
FIGS. 2 and 3
(charge pump). By virtue of the fact that both delay devices
5
(delay lines) are driven with the same control voltages
19
,
20
, an identical delay time results therefrom for both devices.
SUMMARY
It is an object of the present invention to provide a method for generating two signals with a pre-determined spacing between the mutually corresponding signal edges and a corresponding apparatus whereby it is possible to correct an imprecise duty ratio of an external clock signal to a precise internal clock signal with a duty ratio of, in particular, 0.5.
According to the invention, this object is achieved by means of the app

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