Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2000-12-14
2002-04-16
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S156000
Reexamination Certificate
active
06373309
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates in general to a duty cycle compensation circuit of a delay locked loop (DLL) in a Rambus DRAM. More specifically, the inventions claimed herein feature, in part, a duty cycle compensation circuit of a delay locked loop (DLL) capable of reducing power consumption by reducing the time for escaping from a nap mode and extending the time for maintaining the nap mode. This is accomplished by safely storing information even in case of a long nap mode digitalizing an analog duty information of a clock input signal in the nap mode, and immediately using the information re-analogized from digital information of the clock signal that is stored when escaping from the nap mode.
2. Description of Related Art
A DLL circuit which is part of a system receives an externally generated clock signal input, synchronizes it with a clock signal generated within the system, and outputs it. The DLL may be applied to a cash memory unit (‘SRAM’ is generally used.) increasing a data process speed between the CPU of a computer and a DRAM as well as various kinds of logical devices or to a synchronous DRAM and a Rambus DRAM. The duty cycle compensation circuit used in the DLL is a circuit that compensates a duty of an inner clock used in a direct Rambus DRAM.
In general, the Rambus DRAM has various modes of operation such as, for example, active mode, standby mode, and nap mode to operate a system with low electric power drain. Rambus DRAM in operating in its active mode is ready to transmit data at any time and consumes more electric power than it does in its other modes of operation.
In a general DRAM memory system, all memory banks of respective devices consume electric power for reading/writing through the over-all access command, while in the Rambus DRAM memory system, reading/writing are performed through only one device after the other devices are converted into a state of low electric power.
Rambus DRAM is automatically changes to standby mode operation at the last step of transmission. When a request packet is decoded so as to specify the address of a particular device, the other (non-addressed) Rambus DRAMs return to the standby mode, leaving only the addressed device in a more active mode. The addressed device returns to the standby mode when the reading or writing operation ends.
In other words, Rambus DRAMs tend to return to the standby mode. Due to this default mode property, the other Rambus DRAMS remain on the standby mode while only a selected Rambus DRAM changes to active mode operation, thereby minimizing consumption of electric power.
Causing one or more Rambus DRAMs to operate in a nap mode may reduce the consumption of electric power. Nap mode operation consumes less electric power than standby mode operation. A device can change from nap mode to active mode faster than it can change from powerdown mode to active mode. Whenever the system is not reading or writing, the Rambus DRAM changes its mode of operation to nap mode thereby largely reducing the consumption of electric power. When one or more Rambus DRAMS change to power down mode, the greater effect of reduction in electric power can be obtained.
When the Rambus DRAM is in the nap mode, all bias power is off and no inner clock is generated. However, all bias power is on when escaping from the nap mode thereby generating an inner clock.
FIG. 1
shows a known circuit arrangement having a power save mode function for a Rambus DRAM. The circuit arrangement includes a packet controller
200
, a power mode controller
300
, a DLL
400
, and a memory core
100
. The packet controller
200
receives a control packet signal ctrl
13
PKT applied from the external channel of the memory and generates a control signal cntrl controlling whether the power mode is possible or not and an OP_code defining each operation mode.
The power mode controller
300
respectively generates a self refresh enable signal_self_refresh en and power mode signals (a nap mode signal Nap and a power down mode signal PDN) by combining the signals (OP_code and the cntrl) from the packet controller
200
. At this time, the self-refresh enable signal self_refresh_en performs a self-refresh operation by operating the refresh counter (not shown) provided at the inside or outside of the memory core
100
.
Meanwhile, the nap mode signal Nap and the power down mode signal PDN from the power mode controller
300
are transmitted to the DLL
400
thereby controlling the operation of the DLL
400
depending on each power mode.
The DLL
400
is controlled by the nap mode signal Nap and the power down mode signal PDN, receives the clock signal clk_in from the external channel, detects the phase difference between the clock signal clk_in and the clock signal used in a semiconductor memory, adjusts them so that no phase difference exists, and generates a locked signal showing the possibility to be changed to a normal operation mode by the power mode controller
300
.
FIG. 2
is a block construction diagram of the DLL
400
shown in FIG.
1
. DLL
400
comprises a control unit
410
, a bias generation unit
420
, a duty cycle compensation unit
430
, a phase detection and mix unit
440
, a clock amplification unit
450
, and a clock buffer unit
460
.
The phase detection and mix unit
440
receives the clock signal clk_in from the external channel, and outputs a signal obtained by detecting the phase difference between a clock signal clk_in from the external channel and the clock signal clk_out used in the semiconductor memory and mixing the clock signals clk_in and clk_out.
The clock amplification unit
450
amplifies the output signal from the phase detection and mix unit
440
, and outputs the amplified signal to the clock buffer unit
460
. The duty cycle compensation unit
430
compensates for the phase difference between the clock signal clk_in the clock signal clk_out by the PDM signal from the control unit
410
, and stores duty information into a capacitor by the nap mode signal from the control unit
410
. The bias generation unit
420
is operated by the nap mode signal from the control unit
410
and generates a bias signal. The control unit
410
controls the operation of each circuit by the nap mode signal Nap and the power down mode signal PDN from the power mode controller
300
.
FIG. 3
is a circuit diagram of the duty cycle compensation unit
430
shown in FIG.
2
. The duty cycle compensation unit
430
comprises a differential amplification stage
432
controlling output signals in the nap mode (napb signal is ‘low’) and respectively outputting the differentially amplified signals of the input clock signals (clki and clkib) to output nodes (Nd
6
and Nd
7
) in the other operation modes (napb signal is ‘high’), a signal transmission switching stage
434
respectively switching output signals from the differential amplification stage
432
to a first terminal as a signal dccb and a second terminal as a signal dcc, and a storage capacitor stage
436
storing the data signals dccb and dcc.
The differential amplification stage
432
is operated by a signal vbiasn from the bias generation unit
420
, differentially amplifies clock signals clki and clkib when a power reset signal PwrRst is ‘low’, a nap mode bar signal napb is ‘high’, and a capacitor on signal capon is ‘high’, and outputs the amplified signal to the output terminals.
The detailed operation of the differential amplification stage
432
will now be described. First, when the signal vbiasn is enabled to a ‘high’ level, NMOS transistors N
3
, N
4
, and N
5
and PMOS transistors P
1
to P
3
functioning as a current source are turned on thereby operating the differential amplification stage
432
.
Afterwards, when the nap mode bar signal napb is ‘high’ level (not in the nap mode but in the other operation modes), a NMOS transistor N
6
is turned on and the potential level at the node Nd
5
is dropped to a ground potential level Vss through NMOS transistors N
5
and N
6
which are turned on. As the potential level at the node N
5
Hyundai Electronics Industries Co,. Ltd.
Nguyen Linh
Pillsbury & Winthrop LLP
Wells Kenneth B.
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