Duty cycle calibration for receiver clock

Details Duty cycle calibration for receiver clock Duty cycle calibration for receiver clock

2007-12-06

2010-02-23

Raymond, Edward (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system

Measured signal processing

C702S079000, C327S141000, C327S175000, C327S291000, C330S258000, C714S731000, C375S295000, C375S316000, C375S377000

Reexamination Certificate

active

07668698

ABSTRACT:
Embodiments of the invention are generally directed to systems, methods, and apparatuses for the direct duty cycle calibration of a receiver clock. In some embodiments, an integrated circuit includes a receive (RX) data path, a RX clock path, and a control path. In some embodiments, the control path uses RX latches, a majority detector, and digital duty cycle control logic to calibrate the duty cycle of the clock signal. Other embodiments are described and claimed.

REFERENCES:
patent: 6084452 (2000-07-01), Drost et al.
patent: 7202722 (2007-04-01), Mahadevan et al.
patent: 2007/0266285 (2007-11-01), Boerstler et al.
patent: 2008/0013668 (2008-01-01), Willis

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