Duty correction circuit

Details Duty correction circuit Duty correction circuit

2011-05-17

2011-05-17

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S172000

Reexamination Certificate

active

07944262

ABSTRACT:
A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage.

REFERENCES:
patent: 6198322 (2001-03-01), Yoshimura
patent: 6940328 (2005-09-01), Lin
patent: 2000-68797 (2000-03-01), None

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