Duty adjustment circuit

Details Duty adjustment circuit Duty adjustment circuit

2007-02-06

2007-02-06

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S116000

Reexamination Certificate

active

11058635

ABSTRACT:
In a duty adjustment circuit, a clock signal is frequency-divided to ½nby a frequency divider. In a first frequency doubler among n cascade-connected frequency doublers, the divided clock signal is delayed by a variable delay portion according to a control signal. The exclusive logical sum of the delayed signal and the divided clock signal in the frequency-doubling portion doubles the frequency. The average voltage of the frequency-doubled signal is detected by an average value detection portion, and is compared with a reference voltage by a comparison control portion. A control signal is fed back to the variable delay portion to cause the average voltage to become equal to the reference voltage. In this manner, a clock signal is generated from the last frequency doubler with frequency equal to that of the original clock signal, and with duty ratio adjusted to a desired value.

REFERENCES:
patent: 6426660 (2002-07-01), Ho et al.
patent: 6456660 (2002-09-01), Yokoyama
patent: 2003/0184350 (2003-10-01), Wang et al.
patent: 10-163823 (1998-06-01), None

Affiliated with

Also associated with

Rating

Duty adjustment circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Duty adjustment circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Duty adjustment circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3812320