Duration-sensitive digital signal stretcher

Details Duration-sensitive digital signal stretcher Duration-sensitive digital signal stretcher

1985-04-18

1987-01-13

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328112, 307234, 307267, 307602, H03K 5153

Patent

active

046367357

ABSTRACT:
Clocked control signals are applied from a source to the input of delay means having a plurality of successive signal takeoff points, with the delay between successive ones of said takeoff points being the same (e.g., a period at the signal clocking frequency, f.sub.CL). An "and" gate is provided with a plurality of inputs equal in number to the plurality of takeoff points. Each takeoff point is linked by a signal path to a respectively different one of the "and" gate inputs. A succession of two-input "or" gates is provided, with one input of each "or" gate coupled to receive the output of the "and" gate. The last of the succession of "or" gates is coupled to a control signal output terminal. The output of each of the remainder of said succession is coupled via a respectively different one of a plurality of similar delay devices to the other input of the next succeeding one of said succession of "or" gates. Each of the delay devices imparts a delay equal to a period at f.sub.CL. The other input of the first of said succession of "or" gates is coupled to directly receive the control signal source output.

REFERENCES:
patent: 3379981 (1968-04-01), Humpherys
patent: 3614632 (1971-10-01), Leibowitz et al.
patent: 3667054 (1972-05-01), Nelson
patent: 4061975 (1977-12-01), Sugai
patent: 4200810 (1980-04-01), Cain et al.
patent: 4214270 (1980-07-01), Morito
patent: 4233525 (1980-11-01), Tatahashi et al.

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