Multiplex communications – Channel assignment techniques – Carrier sense multiple access
Reexamination Certificate
1998-09-10
2003-04-08
Rao, Seema S. (Department: 2666)
Multiplex communications
Channel assignment techniques
Carrier sense multiple access
C370S462000, C710S240000, C710S308000, C711S100000
Reexamination Certificate
active
06546019
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a duplex memory control circuit used in a data exchange or the like.
2. Description of the Related Art
conventionally, in the filed of data communication, a plurality of terminal units are connected to an exchange, and data transmitted between the terminal units are relayed by the exchange. As a result, the system down of the exchange during communication leads to the interruption of communication. Therefore, the system down of the exchange must be prevented as much as possible.
Under the above circumstances, the exchange is equipped with two data transmission paths of a main system (operating system) and a sub system (preliminary system). During usual operation, data is relayed by using the data transmission path of the main system. Then, when a fault occurs in the main system, the data transmission path is instantly switched over from the main system to the sub system, and the relay of data is continued by using the data transmission path of the sub system. In this way, it is prevented to interrupt communication caused by the system down of the exchange.
For achieving the above function, there are provided two control units for controlling the respective data transmission paths of the main system and sub system. The respective control units are designed such that the control unit of the sub system operates as the control unit of the main system when the main system is switched for the data transmission to the sub system. Therefore, memories equipped in the respective control units store the same data therein at all times (duplex memories).
FIG. 8
is a diagram showing a structural example of a control unit X of the main system and a control unit Y of the sub system (called “duplex memory control apparatus”), which is the above-described duplex memory. In
FIG. 8
, the control unit X includes a CPU
1
a
, a DMAC (direct memory access controller)
2
a
, a memory controller
3
a
connected with a memory
6
a
and a duplex controller
4
a
, and those are connected to each other through a bus B
1
. The CPU
1
a
and the DMAC
2
a
store data delivered from respective paths in the memory
6
a
. The control unit Y is connected to the control unit X through a bus and identical in construction with the control unit Y.
In the control units X and Y shown in
FIG. 8
, data to be processed by the CPU
1
a
is inputted to the bus B
1
of the control unit X, the CPU
1
a
gives a write command to the memory controller
3
a
. In response to this, the memory controller
3
a
writes the data in the memory
6
a
. Then, the duplex controller
4
a
detects the above write command from the bus B
1
, stores the above data and its address (write position) in a TxFIFO
5
a
, and transfers the data and the address to the duplex controller
4
b
of the control unit Y.
The duplex controller
4
b
stores in the RxFIFO
5
b
with the data and the address which are received from the duplex controller
4
a
. In response to this, the DMAC
2
b
is activated and gives the write command of data stored in the RxFIFO
5
b
to the memory controller
3
b
. Then, the memory controller
3
b
writes the above data in the memory
6
b
in accordance with the address stored in the RxFIFO
5
b
. In this way, the same data is written at the same position in the respective memories
6
a
and
6
b.
However, the duplex memory unit (control units X and Y) shown in
FIG. 8
suffers from problems as stated below. That is, in the control units X and Y shown in
FIG. 8
, in the case where a data write command is issued to the CPU
1
a
, there is a case in which the CPU
1
a
must wait for data write processing if the DMAC
2
a
employs the bus B
1
. Also, there is a case in which the DMAC
2
a
accesses to the bus B
1
during the data write processing by the CPU
1
a
, whereby the data write processing of the CPU
1
a
must be interrupted. As a result, there is a case in which a period of time is required for storing data in the memory
6
a
and also for transmitting the data to the control unit Y.
In addition, similarly, in the control unit Y, the CPU
1
b
and the DMAC
2
b
commonly employ the bus B
2
. Therefore, there is a case in which the waiting for or the interruption of the data write processing is caused by the DMAC
2
b
. Accordingly, there is a case in which a period of time is required until the data is stored in the memory
6
a
since the data is transmitted to the control unit
10
b
. In other words, there is a case in which a period of time is required until the contents in the memory
6
a
becomes identical with those in the memory
6
b.
However, it takes time to make the contents in both the memories
6
a
and
6
b
identical with each other, therefore, when the system is switched from the main system to the sub system, there exists data that has been stored in the memory
6
a
but has not yet been stored in the memory
6
b
. As a result, there is a possibility in that a communication trouble occurs because the data is not stored in the memory
6
b.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problems with the conventional unit, and therefore an object of the present invention is to provide a duplex memory control apparatus which is capable of making the contents stored in the respective memories identical with each other quicker than the conventional one.
In order to solve the above problems, a duplex memory control apparatus of the present invention comprises a first control unit containing a first memory and a second control unit containing second memory, the first control unit and the second control unit connected to each other through a bus. The first control unit includes a central processing unit writing write data in the first memory; a transmitter obtaining the write data to be written in the first memory by the central processing unit, the transmitter, when the write data can be specified based on another write data previously obtained, transmitting specific data smaller than the write data to the second control unit instead of the write data; a first bus mutually connecting the central processing unit, the first memory and the transmitter; a first direct memory access unit reading the write data held in the first memory through the first bus; a second bus connected with the first direct memory access unit; and an access limiter connected to the first bus and the second bus and limiting to use the first bus by the first direct memory access unit when the central processing unit uses the first bus. The second control unit includes a data producing section receiving the specific data from the transmitter and producing an original write data based on the specific data; and a second direct memory access unit writing the original write data produced by the data producing section into the second memory.
According to the present invention, in the first control unit, when the central processing unit writes the data in the first memory through the first bus, the use of the first bus by the first direct memory access unit is limited by the access limiter. Also, the transmitter obtains the data which is written in the first memory and judges whether the data can be specified by the data which has been obtained before, or not. In this situation, when the data can be specified, the specific data is transmitted to the second control unit instead of the data. In the second control unit, the data producing section produces the original data from the specific data received from the transmitter. Then, the second direct access memory unit writes the data produced by the data producing section in the second memory.
According to the present invention, since the first direct memory access unit can be prevented from accessing to the first bus when the central processing unit writes the data in the first memory, there is no case of waiting for or interrupting the data write processing. Also, the transmitter transfers the specific data to the second control unit instead of the data per se. Therefor
Iwasa Hidetoshi
Kato Yoshiharu
Mitsuze Kiyofumi
Takajitsuko Ryo
Fujitsu Limited
Mehra Inder Pal
Rao Seema S.
Staas & Halsey , LLP
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