Duo-binary and/or binary data slicer

Details Duo-binary and/or binary data slicer Duo-binary and/or binary data slicer

1992-02-19

1994-02-22

Groody, James J.

Television

Format

Including additional information

307350, 307351, 307352, H04N 708

Patent

active

052892786

ABSTRACT:
A duo-binary and/or binary data slicer has a data input (10) coupled via a capacitor (C1) to a d.c. restoring circuit (A2 to Q6 and Q9 to Q13) d.c. reference level is superimposed on the data signal. A sample and hold circuit (C2, Q15 to Q22) is arranged to sample the data signal and provide a voltage related to the upper and lower peak value. A divider (R16-R19) is coupled between the d.c. reference level and the voltage related to the upper and lower peak value and provides intermediate output voltages (DU, DL, B) relating to duo-binary and/or binary level for determining the slicing levels.

REFERENCES:
patent: 3600688 (1971-08-01), Booth
patent: 3611164 (1971-10-01), Day
patent: 4581544 (1986-04-01), Feldman
patent: 4703354 (1987-10-01), Auld
patent: 4707730 (1987-11-01), Alard
patent: 4859872 (1989-08-01), Hyakutake
patent: 4912420 (1990-05-01), Parnell

Affiliated with

Also associated with

Rating

Duo-binary and/or binary data slicer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Duo-binary and/or binary data slicer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Duo-binary and/or binary data slicer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-175950