Dummy underlayers for improvement in removal rate consistency du

Fishing – trapping – and vermin destroying

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437190, 437195, 437225, 437228, H01L 21302, H01L 21463

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active

056396970

ABSTRACT:
A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

REFERENCES:
patent: 4916514 (1990-04-01), Nowak
patent: 5476817 (1995-12-01), Numata
Ichikawa, et al., "Multilevel Interconnect System for 0.35um CMOS Lsi's with Metal Dummy Planarization Process and Thin Tungsten Wirings", Jun. 27-29, VMIC Conference, 1995 ISMIC--104/95/0254.

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