Coded data generation or conversion – Converter calibration or testing – Trimming control circuits
Patent
1989-10-24
1990-08-07
Shoop, Jr., William M.
Coded data generation or conversion
Converter calibration or testing
Trimming control circuits
341118, 341120, H03M 106
Patent
active
049471694
ABSTRACT:
In one embodiment, a successive approximation analog-to-digital converter having a main CDAC and a trim CDAC includes resistors in the main CDAC connected in series with various bit switch FETs. The resistors are precisely matched to equivalent resistances of trimmable voltage divider circuits connected in series with various corresponding bit switch FETs in the trim DAC, to prevent non-linear parasitic capactiance and voltage-current properties of first and second clamping FETs from "unbalancing" the voltages on the charge summing conductors of the main DAC and the trim DAC during turn-off of the first and second clamping FETs after they have been turned on to equalize the voltages of the charge summing conductors. In another embodiment, separate trim and dummy DACs are provided to improve the accuracy to which the resistances in the main CDAC and trim CDAC can, as a practical matter, be matched.
REFERENCES:
patent: 4138671 (1979-02-01), Comer et al.
patent: 4150366 (1979-04-01), Price
patent: 4222107 (1980-09-01), Mrozowski et al.
patent: 4272760 (1981-06-01), Prazak et al.
patent: 4335371 (1982-06-01), Connolly, Jr. et al.
patent: 4338590 (1982-07-01), Connolly, Jr. et al.
patent: 4344067 (1982-08-01), Lee
patent: 4523182 (1985-06-01), Harvey et al.
patent: 4568917 (1986-02-01), McKenzie et al.
patent: 4584568 (1986-04-01), Zomorrodi
patent: 4616212 (1986-10-01), Law et al.
patent: 4618852 (1986-10-01), Kelly et al.
patent: 4647906 (1987-03-01), Naylor et al.
patent: 4851838 (1989-07-01), Shier
"A Charge-Transfer Multiplying Digital-to-Analog Converter", by Jose F. Albarran and David A. Hodges, reprinted from IEEE J. Solid-State Circuits, vol. SC-11, pp. 772-779, Dec. 1976, (pp. 129-136).
Smith Lewis R.
Thomas David M.
Burr-Brown Corporation
Shoop Jr. William M.
Young Brian K.
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