Dummy structures that protect circuit elements during polishing

Details Dummy structures that protect circuit elements during polishing Dummy structures that protect circuit elements during polishing

2001-04-30

2003-05-06

Coleman, William David (Department: 2823)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S926000

Reexamination Certificate

active

06559055

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to fabrication of integrated circuits, and more particularly to use of polishing processes, such as chemical mechanical polishing (CMP), in the fabrication of integrated circuits.
CMP is widely used to planarize the top surface of a dielectric layer before the dielectric is patterned or subsequent layers are deposited. Planarization is desirable because it relaxes the depth of focus requirements for photolithographic equipment used to pattern the dielectric layer or the overlying layers. If the top surface of the dielectric is planar, greater variation of the depth of focus can be tolerated. This is especially important if the photolithographic equipment has to create small geometries.
CMP is widely used for planarization because CMP is fast and does not require high temperatures.
SUMMARY
Chemical mechanical polishing of a dielectric layer typically stops on a harder layer underlying the dielectric layer. For example, CMP of silicon dioxide can stop on silicon nitride deposited before the silicon dioxide. See U.S. Pat. No. 5,909,628, issued Jun. 1, 1999, entitled “REDUCING NON-UNIFORMITY IN A REFILL LAYER THICKNESS FOR A SEMICONDUCTOR DEVICE”.
Some embodiments of the present invention relate to integrated circuits which have circuit elements formed from different conductive or semiconductor layers. For example, an integrated circuit may have transistor gates formed from different polysilicon layers. A dielectric overlies these polysilicon layers, and is polished by CMP. A harder layer is formed over the polysilicon layers underneath the dielectric layer. CMP stops on the harder layer. For example, the dielectric polished by CMP can be silicon dioxide, and the harder layer can be silicon nitride. The harder layer is patterned to form protective features over one of the polysilicon layers (“first polysilicon layer”) but not over the other one of the polysilicon layers (“second polysilicon layer”). Dummy structures are formed from the first polysilicon layer adjacent to the transistor gates formed from the second polysilicon layer. Dummy structures include portions of the first polysilicon layer and portions of the harder layer. The harder layer portions protect the transistor gates formed from the second polysilicon layer from being exposed during the polishing.
In some embodiments, the first and second polysilicon layers also provide capacitor plates in the integrated circuit. In some embodiments, the circuit processes analog signals and, possibly, also digital signals.
The invention is not limited to transistors gates or capacitor plates. The invention is not limited to polysilicon, silicon dioxide, silicon nitride, or any other particular materials. In some embodiments, a method for fabricating an integrated circuit comprises: forming a first layer over a semiconductor substrate, the first layer providing at least a portion of a first circuit element and at least a portion of a dummy element; forming a second layer over the semiconductor substrate, the second layer providing at least a portion of a second circuit element; forming a protective feature from a third layer over the first circuit element and the dummy element but not over the second circuit element; forming a dielectric layer over the first, second and third layers; and polishing the dielectric layer by a polishing process that stops on the third layer, such that the protective feature over the dummy element protects the second element during the polishing process.
Other features and advantages of the invention are described below.


REFERENCES:
patent: 4794565 (1988-12-01), Wu et al.
patent: 5029130 (1991-07-01), Yeh
patent: 5045488 (1991-09-01), Yeh
patent: 5067108 (1991-11-01), Jenq
patent: 5120671 (1992-06-01), Tang et al.
patent: 5202850 (1993-04-01), Jenq
patent: 5212541 (1993-05-01), Bergemont
patent: 5217920 (1993-06-01), Mattox et al.
patent: 5242848 (1993-09-01), Yeh
patent: 5264387 (1993-11-01), Beyer et al.
patent: 5265059 (1993-11-01), Wells et al.
patent: 5278087 (1994-01-01), Jenq
patent: 5376573 (1994-12-01), Richart et al.
patent: 5399516 (1995-03-01), Bergendahl et al.
patent: 5479368 (1995-12-01), Keshtbod
patent: 5543339 (1996-08-01), Roth et al.
patent: 5576232 (1996-11-01), Hong
patent: 5587332 (1996-12-01), Chang et al.
patent: 5616941 (1997-04-01), Roth et al.
patent: 5640031 (1997-06-01), Keshtbod
patent: 5661053 (1997-08-01), Yuan
patent: 5668757 (1997-09-01), Jeng
patent: 5696019 (1997-12-01), Chang
patent: 5712179 (1998-01-01), Yuan
patent: 5736442 (1998-04-01), Mori
patent: 5763309 (1998-06-01), Chang
patent: 5770501 (1998-06-01), Hong
patent: 5776787 (1998-07-01), Keshtbod
patent: 5851879 (1998-12-01), Lin et al.
patent: 5856943 (1999-01-01), Jeng
patent: 5909628 (1999-06-01), Chatterjee et al.
patent: 5912843 (1999-06-01), Jeng
patent: 5943261 (1999-08-01), Lee
patent: 5953255 (1999-09-01), Lee
patent: 5963473 (1999-10-01), Norman
patent: 5965913 (1999-10-01), Yuan et al.
patent: 5991204 (1999-11-01), Chang
patent: 6001687 (1999-12-01), Chu et al.
patent: 6001706 (1999-12-01), Tan et al.
patent: 6013551 (2000-01-01), Chen et al.
patent: 6025229 (2000-02-01), Hong
patent: 6027971 (2000-02-01), Cho et al.
patent: 6028336 (2000-02-01), Yuan
patent: 6043530 (2000-03-01), Chang
patent: 6043536 (2000-03-01), Numata et al.
patent: 6054355 (2000-04-01), Inumiya et al.
patent: 6057572 (2000-05-01), Ito et al.
patent: 6057575 (2000-05-01), Jenq
patent: 6066544 (2000-05-01), Pan et al.
patent: 6087208 (2000-07-01), Krivokapic et al.
patent: 6103592 (2000-08-01), Levy et al.
patent: 6108236 (2000-08-01), Barnett
patent: 6165692 (2000-12-01), Kanai et al.
patent: 6166415 (2000-12-01), Sakemi et al.
patent: 6169012 (2001-01-01), Chen et al.
patent: 6171910 (2001-01-01), Hobbs et al.
patent: 6171971 (2001-01-01), Natzle
patent: 6171976 (2001-01-01), Cheng
patent: 6177303 (2001-01-01), Schmitz et al.
patent: 6191001 (2001-02-01), Chen et al.
patent: 6191049 (2001-02-01), Song
patent: 6191444 (2001-02-01), Clampitt et al.
patent: 6228715 (2001-05-01), Shimoji
patent: 6248630 (2001-06-01), Clementi et al.
patent: 6266277 (2001-07-01), Roohparvar
patent: 6316293 (2001-11-01), Fang
patent: 6355524 (2002-03-01), Tuan et al.
patent: 6392928 (2002-05-01), Roohparvar
patent: 6403417 (2002-06-01), Chien et al.
“A Review of 256Mbit NAND Flash Memories and NAND Flash Future Trend”,Riichiro Shirota(Microelectronics Engineering Laboratory), unknown date before Aug. 15, 2000, pp. 22-31.
“A Novel High-Density 5F2NAND STI Cell Technology Suitable for 256Mbit and 1 Gbit Flash Memories”,K. Shimizu, K. Narita, H. Watanabe, E. Kamiya, Y. Takeuchi, T. Yaegashi, S. Aritome, and T. Watanabe, (IEEE Tech. Dig. Dec. 7-10, 1997, pp. 271-274), pp. 11.1.1-11.1.4.
“A New Flash-Erase EEProm Cell With a Sidewall Select-Gate On Its Source Side”,K. Naruke, S. Yamada, E. Obi, S. Taguchi, and M. Wada, (IEDM Tech. Dig. Dec. 3-6, 1989, PP, 603-606), pp. 25.7.1-25.7.4.
“A 0.67 mn2Self-Aligned Shallow Trench Isolation Cell (SA-STI Cell) For 3V—only 256Mbit Nand EEPROMs”,S. Aritome, S. Satoch, T. Maruyama, H. Watanabe, S. Shuto, G.J. Hemink, R. Shirota, S. Watanabe and F. Masuoka, (IEDM Tech. Dig. Dec. 11-14, 1994, PP. 61-64), pp. 3.6.1-3.6.4.
“A Novel High-Speed, 5-Volt Programming Eprom Structure With Source-Side Injection”,A.T. Wu, T.Y. Chan, P.K. Ko and C. Hu(IEDM Tech. Dig., pp. 584-587, 1986), pp. 108-111.
“Nonvolatile Semiconductor Memory Technology” “A Comprehensive Guide to Understanding and Using NVSM Devices”,William D. Brown, Joe E. Brewer(IEEE Press series on microelectronic systems 1998), pp. 21-23.
Naruke et al., “A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on its Source Side”, IEDM Tech. Dig. Dec. 1989, pp. 603-606.

Affiliated with

Also associated with

Rating

Dummy structures that protect circuit elements during polishing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dummy structures that protect circuit elements during polishing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dummy structures that protect circuit elements during polishing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3059337