Dummy columns for reducing pattern sensitivity in MOS/LSI dynami

Details Dummy columns for reducing pattern sensitivity in MOS/LSI dynami Dummy columns for reducing pattern sensitivity in MOS/LSI dynami

1979-10-11

1982-07-13

Munson, Gene M.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 23, 365149, H01L 2702, H01L 2978, G11C 1124

Patent

active

043397662

ABSTRACT:
An MOS/LSI type dynamic RAM with single 5V supply and grounded substrate employs a pair of dummy columns on each end of the cell array to prevent pattern sensitivity in testing. The dummy columns have capacitors which alternate between large and small so a given cell will always read a "1" or "0" upon refresh. These cells are not accessed in normal read or write cycles. Thus, regardless of the row addressed, one column line half on each side will go high and the other low. This shields the ends of the array from diffusing electrons (minority carriers).

REFERENCES:
patent: 4112508 (1978-09-01), Itoh
patent: 4118794 (1978-10-01), Mizuno et al.
patent: 4198697 (1980-04-01), Kuo et al.

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