Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2000-10-17
2002-08-27
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S760020, C324S765010
Reexamination Certificate
active
06441606
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to an apparatus for testing semiconductor devices, and more particularly to an apparatus providing dual temperature zone dynamic wafer-level burn-in of semiconductor devices.
Testing of semiconductor devices during the numerous steps involved in their fabrication occurs at various points along the process to determine proper circuit operability. Two of the more prevalent places to conduct such electrical tests are first at the wafer level, where an integrated circuit (IC) semiconductor device is formed, along with hundreds of others, on a six, eight or twelve inch diameter circular wafer of doped silicon, and second, at the IC level, where individual ICs, known singularly and collectively as “die” and “dice” respectively, are cut from the wafer and tested either in a “bare” or “encapsulated” state prior to shipping. A critical part of the first type of testing (i.e.: wafer level) involves so-called “probe” testing, where connections between each interconnect, or pad, on a device on a wafer and the testing apparatus are temporarily made to provide a communication path through which preprogrammed test signals are passed.
Once the ICs are separated from the wafer, an elevated temperature “burn-in” operation is employed to subject the IC to a further battery of tests, thus providing a better indication that the device will function for its intended purpose. Burn-in testing is used to accelerate the identification and isolation of semiconductor devices prone to infant mortality failure mechanisms. During elevated-temperature burn-in testing, stable, precise control of the test chamber is required to ensure, among other things, that adequate impurity migration (which accounts for a significant portion of device infant mortality) is accounted for. However, burn-in testing can be a significant factor in the cost of processing of semiconductor devices. In an era where customer demands to simultaneously increase semiconductor reliability and reduce prices continues apace, manufacturers have been forced to look to increasingly innovative ways to lower the expense of device manufacture while still providing the high-quality products their customers have come to expect.
Traditional burn-in testing has been at the packaged device level, where the use of specialized burn-in boards and sockets is prevalent. Properly engineered boards and sockets, with their complex interconnection schemes and setup, increases testing time and expense. Thus, wafer level burn-in testing can provide a much quicker, less expensive way to determine if a significant number of ICs on a single wafer are worthy of being diced, individually packaged, and then subjected to more detailed operational tests. Dynamic burn-in testing at the wafer level is one of the ways, along with static and full-functional, or “intelligent” burn-in, to maximize the likelihood that a batch of semiconductor devices will survive in an end-use product, while keeping the costs to a minimum.
However, the emergence of wafer level testing has not alleviated all of the problems of die level testing. Current wafer burn-in approaches have wafers connected to rack or oven mounted control system tester/drive electronics. If a portion of the test electronics experiences a malfunction, the entire oven must be shut down to remove or repair the defective electronic module. Additional down-time can result from routine thermal circuit connections made each time a cassette holding a wafer under test is inserted into a rack or oven. For example, when a single (i.e.: non-removable) fixture with multiple temperature control feed lines is utilized, such an approach is inconvenient and time-consuming from a test standpoint, as each time a wafer needs to be inserted or removed from the test area, the thermal circuits attached to the wafer cassette must be disconnected, as the integral nature of the wafer cassette and housing necessitate removal of both to access and remove the wafer. The potential for damage to the connectors under such an approach is great, especially after repeated use.
Testing systems are used in many of the stages of the semiconductor fabrication process. In some instances, these stages are carried out over numerous individual machines, while in others, within a single integrated apparatus. Inside wafer level burn-in systems are coming to market. In such systems, wafers are supported in a wafer cassette that secures the wafer under test to maintain precise positional control, thus permitting proper alignment between the individual dies on the wafer and the control electronics. Precise temperature control of wafers under test is required to ensure that actual operating conditions to which an individual die will eventually be exposed in service are accurately replicated. Thermal control systems employing water, air and combinations thereof are both under development and coming to market, in order to keep temperatures in the test area stable for just such purposes. Typically, the test housing in these systems contain the support base, wafer and wafer test fixtures, as well as thermal circuitry. The fluid is routed through thermal circuit penetrations in the support structure walls of the test housing, and is used as a heat transfer mechanism for all of the parts within the housing. It must be pointed out that a thermal circuit responsive to the aggregate needs of the entire cassette may not be suitable to the needs of just the wafer being tested.
In addition, the test electronics are located away from the article being tested, with connection to their remote location effected through coupling cables or the like. This remote positioning of the test electronics inhibits the ability of the burn-in test to adequately support the increasingly faster modem electronic circuits, many of which have a clock time of such short duration that the travel time to and from the remote test electronics is greater than the time between clock cycles. Higher inductance and capacitance occurs when signals must pass through long lines to remotely-spaced electronic devices. This leads to less sharp, well-defined signal transitions, which lead to a compromise in signal integrity. However, merely placing the test electronics adjacent the wafer cassette, without consideration of the wildly varying thermal needs of the test electronics, would only serve to exacerbate an already-perplexing thermal management problem for the wafer under test, as well as potentially jeopardizing sensitive electronic devices.
Accordingly, the need exists in the art for a system which can provide inexpensive, compact and reliable support for wafers during burn-in, especially permitting independent temperature regimes to be tailored to the particular testing needs of the wafer and test electronics, while simultaneously facilitating quick insertion and removal of the wafers under test.
SUMMARY OF THE INVENTION
The present invention satisfies the aforementioned need by providing a system which utilizes a separable wafer cassette and base, on-board test electronics, and a plurality of independent temperature control means for the wafer under test and the test electronics. The stackable, modular features of a wafer cassette separable from a stationary base ensure greater system flexibility to meet myriad testing requirements by facilitating wafer interchangeability without having to disconnect and reconnect the thermal circuits each time a wafer is changed. This is made possible in the present invention by including the thermal circuits and their connectors as integral parts of the base, which is in turn fixed to a chassis in the oven or rack. Moreover, the on-board mounting and attendant close proximity of the test electronics to the wafers being tested ensures maximum test performance at rapid test speeds, as well as a compact package, which is critical when such a package is to be enclosed in the tight confines of a burn-in oven.
According to an aspect of the present invention, a wafer burn-in cassette support comprises at least
Caldwell John
Nuxoll James
Totorica Robert
Killworth, Gottman Hagan & Schaeff LLP
Nguyen Vinh P.
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