Dual write cycle programmable conductor memory system and...

Details Dual write cycle programmable conductor memory system and... Dual write cycle programmable conductor memory system and...

2002-05-03

2004-05-04

Mai, Son (Department: 2818)

Static information storage and retrieval

Read only systems

Resistive

C365S148000, C365S163000, C365S222000

Reexamination Certificate

active

06731528

ABSTRACT:

FIELD OF INVENTION
The present invention relates to integrated memory circuits. More specifically, it relates to a method for writing a programmable conductor random access memory (PCRAM) cell.
BACKGROUND OF THE INVENTION
Dynamic random access memory (DRAM) integrated circuit arrays have existed for more than thirty years and their dramatic increase in storage capacity has been achieved through advances in semiconductor fabrication technology and circuit design technology. The tremendous advances in these two technologies have also achieved higher levels of integration that permit dramatic reductions in memory array size and cost, as well as increased process yield.
FIG. 1
is a schematic diagram of a DRAM memory cell
100
comprising an access transistor
101
and a capacitor
102
. The capacitor
102
, which is coupled to a Vcc/2 potential source and the transistor
101
, stores one bit of data in the form of a charge. Typically, a charge of one polarity (e.g., a charge corresponding to a potential difference across the capacitor
102
of +Vcc/2) is stored in the capacitor
102
to represent a binary “1” while a charge of the opposite polarity (e.g., a charge corresponding to a potential difference across the capacitor
102
of −Vcc/2) represents a binary “0.” The gate of the transistor
101
is coupled to a word line
103
, thereby permitting the word line
103
to control whether the capacitor
102
is conductively coupled via the transistor
101
to a bit line
104
. The default state of each word line
103
is at ground potential, which causes the transistor
101
to be switched off, thereby electrically isolating capacitor
102
.
One of the drawbacks associated with DRAM cells
100
is that the charge on the capacitor
102
may naturally decay over time, even if the capacitor
102
remains electrically isolated. Thus, DRAM cells
100
require periodic refreshing. Additionally, as discussed below, refreshing is also required after a memory cell
100
has been accessed, for example, as part of a read operation.
Efforts continue to identify other forms of memory elements for us in memory cells, particularly for memory elements which do not required frequent refresh operations. Recent studies have focused on resistive materials that can be programmed to exhibit either high or low stable ohmic states. A programmable resistance element of such material could be programmed (set) to a high resistive state to store, for example, a binary “1” data bit or programmed (set) to a low resistive state to store a binary “0,” data bit. The stored data bit could then be read by detecting the magnitude of a readout current switched through the resistive memory element by an access device, thus indicating its programmed stable resistance state.
Recently programmable conductor materials, such as chalcogenide glasses, have been investigated as data storage memory cells for use in memory devices. U.S. Pat. Nos. 5,761,115, 5,896,312, 5,914,893, and 6,084,796 all describe chalcogenide glass materials which can be used as programmable conductor memory elements and are incorporated herein by reference. One characteristic of such an element is that it typically includes a chalcogenide glass which is doped with metal ion and a cathode and anode spaced apart on a surface of the glass. Application of a voltage across the cathode and anode causes the glass to achieve a low resistance state. One theory for this is that the applied voltage causes growth of a nearly non-volatile metal dendrite in or on the surface of the glass which changes the resistance and capacitance of the memory element which can then be used to store data.
One particularly promising programmable conductor material is a chalcogenide glass formed as an alloy system including Ge:Se:Ag for example, a Ge
x
:Se
(1−x)
composition which is doped with silver. A memory element comprised of a chalcogenide glass has a natural stable high resistive state but can be programmed to a low resistance state by passing a current pulse from a voltage of suitable polarity through the cell. A chalcogenide memory element is simply written over by the appropriate current pulse and voltage polarity (reverse of that which writes the cell to a low resistance state) to reprogram it, and thus does not need to be erased. Moreover, a memory element of chalcogenide material is nearly nonvolatile, in that it need only be rarely refreshed in order to retain its programmed low resistance state. Such memory cells, unlike DRAM cells, can be accessed without requiring a refresh.
Since there is a considerable body of known and proven circuitry for reading, writing and refreshing DRAM memory cells, it would be desirable to use the same or similar circuitry with programmable conductor memory elements. However, while conventional read sense amplifier circuitry, associated with DRAM cells, are capable of use in accessing and sensing programmable element random access memory (PCRAM) cells, the natural refresh operation associated with these sense amplifiers is not required for a programmable conductor memory element. Indeed, frequent rewriting of PCRAM memory elements to the same state is not desirable because it can cause the memory element to wear out faster. Accordingly, there is a need and desire for a circuit and method for writing PCRAM cells without causing premature deterioration.
SUMMARY OF THE INVENTION
The present invention provides an improved method for reading a programmable conductor memory element which reduces premature deterioration due to repeated refresh operations. This is accomplished by first performing a read operation on a memory element and then writing the memory element to the opposite or complement logical state from the state which was read and then writing the memory element back to the original logical state. Hence, if following a high resistance state read operation the memory element is to be written to a high resistance state, then the memory element is first written to the opposite state (i.e., low resistance state) and then written back to the original state (i.e., high resistance state). Alternatively, if following a low resistance state read operation the PCRAM cells are to be written to a low resistance state, then the cells are first written to the opposite state (i.e., high resistance state) and then written back to the original state (i.e., low resistance state).
In an alternative embodiment, after a read operation the memory element may simply be re-written to a state complementary to the read state and logic circuitry associated with a memory device containing the memory element keeps track during a read operation if the read data should output as read or after being inverted. For example, if a high resistance state represents a “1” data value and a low resistance state represents a “0” data value, and if a memory element is read as a “1” that memory element will be written to a “0” state following the read operation. During a subsequent read of the same memory element, as a “0” the logic circuitry will invert the logic state and output it correctly as a “1.” After the subsequent read, the memory element will then be written to a “1” state and the logic circuit will note that no logical state inversion is required for the next read of the memory element.


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