Dual wafer attachment process

Details Dual wafer attachment process Dual wafer attachment process

1999-08-02

2001-09-11

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

C438S458000, C438S107000, C438S118000

Reexamination Certificate

active

06287940

ABSTRACT:

The invention pertains to microstructure wafers. Particularly, it pertains to attachment of wafers, and more particularly to temperature sensitive wafers.
The invention involves the bonding of devices or materials fabricated on separate wafers. A microstructure's front surface may be bonded to another microstructure; however, a microstructure on one substrate may be incompatible with the process used to produce the other microstructure. The invention is designed to avoid problems caused by such incompatibility.
The need for such a process is driven by the performance needs in several areas of military and industrial applications, including thermal and mechanical sensors, magnetoresistive memory arrays, and superconducting channels.
Wafer bonding technology has existed for some time. Therefore, other patented processes exist producing more and less similar structures. The idea of bonding wafers processed with incompatible processes has been tried. Existing bolometer technology requires that the readout electronics, CMOS and metalizations survive the processing conditions used for the detector materials. The development of high temperature coefficient of resistance (TCR) materials, which require very high processing temperature, provided an incentive to develop a technique for coupling these materials into bolometer technology. The present technique is superior to related art single-wafer technology because the detector film is processed at temperatures much higher than 450 degrees Celsius (C.), which is the practical limit of CMOS devices.
SUMMARY OF THE INVENTION
The present invention consists of producing the desired microstructures on separate substrates and coating them with a suitable bonding material. These structures may be CMOS electronics or a pure microstructure. One embodiment includes a high-temperature thermal sensor on one wafer and low-temperature CMOS electronics with some electrical and thermal features on another wafer. In the case where the bonding material is polyimide, the polyimide on both surfaces to be bonded are soft baked. The wafers are placed in a wafer bonder and, using precision alignment, brought into contact. The application of pressure and heat forms a bond between the two coatings of polyimide.
A wafer may need to be removed from a combined structure. A particularly advantageous technique is to build one of the bonded structures on a sacrificial layer that can be etched away to facilitate removal of a wafer without grinding. Further processing can be done on either or both structures.
After wafer removal, a contact from the backside of one of the structures now on polyimide to the other on the wafer has been demonstrated. This contact, electrical or physical, is one of many kinds, which could be made. Sacrificial material, for example, polyimide, may be removed from between the structures that are bonded via a contact. It may also be desirable to bond a microstructure with something that is not a microstructure, such as single- or multi-layer material, crystalline or amorphous. The present process provides a good method of bonding of these items, while incorporating the materials having a temperature coefficient of resistance that range from a typical value of 2%/C to a high value of 3.5%/C on the present wafers. The TCR may be measured at a value of 12%/C on bulk substrates with much lower 1/f (k=10
−14
) noise than VO
x
(vanadium oxide) (k=10
−13
) films. The material may be thinned after wafer removal to improve performance with lower mass.


REFERENCES:
patent: 5173474 (1992-12-01), Connell et al.
patent: 5246880 (1993-09-01), Reele et al.
patent: 5449659 (1995-09-01), Garrison et al.
patent: 5455445 (1995-10-01), Kurtz et al.
patent: 5465009 (1995-11-01), Drabik et al.
patent: 5489554 (1996-02-01), Gates
patent: 5572060 (1996-11-01), Butler et al.
patent: 5574298 (1996-11-01), Hashimoto et al.
patent: 5627106 (1997-05-01), Hsu
patent: 5627112 (1997-05-01), Tennant et al.
patent: 5880010 (1999-03-01), Davidson
patent: 5976953 (1999-11-01), Zavracky et al.
Cole B et al: “Monolithic Two-Dimensional Arrays of Micromachined Microstructures for Infrared Applications” Proceedings of the IEEE, US, IEEE. New York. vol. 86, No. 8, Aug. 1998 (1998-08), pp. 1679-1686, XP000848433, ISSN: 0018-9219, The Whole Document.
Patent Abstracts of Japan, vol. 1999, No. 2, Feb. 26, 1999 & JP 10 303434 A (Murata MFG Co Ltd), Nov. 13, 1998 Abstract.

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