Dual voltage supply circuit with multiplier-controlled transisto

Details Dual voltage supply circuit with multiplier-controlled transisto Dual voltage supply circuit with multiplier-controlled transisto

1991-05-08

1992-03-24

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072968, 307475, 36518909, H03R 1706

Patent

active

050991434

ABSTRACT:
An address decoder circuit adapted for enabling electrical erasure in a non-volatile memory without the necessity of numerically increasing the component elements, wherein the direction of application (polarity) of a supply voltage during an erasing operation to a decoding logic gate portion comprising a load MOS transistor and an address input MOS transistor is rendered different from that during a writing or reading operation, and a third potential is applied to the power terminal proximate to the address input MOS transistor and also to the power terminal of a buffer, whereby the third potential is outputted to prevent erasure in the state of non-selection. The resistance of load means is changed to be greater in a writing operation for reducing the power consumption during the writing operation and minimizing the dimensions of component elements. And in a voltage supply circuit, for the purpose of outputting a desired voltage without providing any additional circuit which may consume great power or without causing any level reduction of a first or write voltage, a MOS transistor for outputting the first voltage is controlled in response to a signal obtained by boosting the voltage of a control signal through a voltage multiplier.

REFERENCES:
patent: 4835423 (1989-05-01), de Ferron et al.
patent: 4916334 (1990-04-01), Minagawa et al.
patent: 4926070 (1990-05-01), Tanaka et al.
patent: 4958091 (1990-09-01), Roberts
patent: 4970409 (1990-11-01), Wada et al.
patent: 5010259 (1991-04-01), Inoue et al.
patent: 5038325 (1991-08-01), Douglas et al.

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