Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2001-07-13
2004-06-08
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S318000, C327S324000
Reexamination Certificate
active
06747501
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains in general to a semiconductor device, and, more particularly, to a dual-triggered electrostatic discharge protection circuit.
2. Description of the Related Art
A semiconductor integrated circuit (IC) is generally susceptible to an electrostatic discharge (ESD) event that may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration in which a large amount of current is discharged through the IC. The high current may be built-up from a variety of sources, such as the human body. Many schemes have been implemented to protect an IC from an ESD event.
A common protection scheme uses a parasitic transistor associated with an n-type metal-oxide semiconductor (NMOS) with the source coupled to ground and the drain connected to an input or output pad from which an ESD current enters to protect an internal circuit. In deep sub-micron complementary metal oxide silicon (CMOS) technology, thin oxides are required. As an oxide layer becomes thinner, the breakdown voltage of the oxide becomes lower. Therefore, an ESD protection scheme must accordingly lower the trigger voltage. The known protection scheme described above is triggered at a level close to that of the oxide breakdown voltage and therefore may be inadequate for ESD protection.
FIG. 1
is a reproduction of FIG. 2 of U.S. Pat. No. 5,631,793 to Ker et al, Ker being one of the inventors of the present invention. Ker et al. describes a capacitor-coupled ESD protection circuit that includes an ESD bypass device
623
to discharge an ESD current, and a capacitor-coupled circuit
622
to couple a portion of the voltage to an ESD clamping device. The ESD bypass device
623
include a PMOS transistor Mp
2
and an NMOS transistor Mn
2
. The substrate of the PMOS transistor Mp
2
is coupled to the source of the PMOS transistor, and the substrate of the NMOS transistor Mn
2
is coupled to the source of the NMOS transistor.
FIG. 2
is a reproduction of FIG. 28 of U.S. Pat. No. 5,811,857 to Assaderaghi et al., entitled “Silicon-on-Insulator Body-Coupled Gated Diode for Electrostatic Discharge (ESD) and Analog Applications.” Assaderaghi et al. describes a clamping device consisting of a MOS transistor having the gate and body (substrate) connected together. As the gate and substrate voltage increase, the threshold voltage of the MOS transistor decreases. Referring to
FIG. 2
, the drain
34
is coupled to a level shifting device
110
, which in turn is coupled to the gate
32
of the MOS transistor
40
. The gate
32
is coupled to the body (or substrate)
38
of the MOS transistor
40
.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a dual-triggered electrostatic discharge protection circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided an electrostatic discharge protection circuit that includes a clamping circuit including a first transistor, the first transistor having a drain, a source, a gate and a substrate, and a control circuit coupled to the clamping circuit, the control circuit being coupled to the gate and substrate of the first transistor and providing a first bias voltage signal to the gate of the first transistor and a second bias voltage signal to the substrate of the first transistor to trigger the clamping circuit to discharge an electrostatic current.
In one aspect of the invention, the first bias voltage is equal to, greater than, or less than the second bias voltage.
In another aspect of the invention, the control circuit comprises a second transistor and at least one diode having a first end and a second end, wherein the second transistor is coupled to the first end of the at least one diode.
Also in accordance with the present invention, there is provided an integrated circuit that includes signal receiving means for receiving an electrostatic signal, clamping means for directing the electrostatic signal to ground, the clamping means having a first end and a second end, the first end being coupled to the signal receiving means and the second end being coupled to ground, and control means coupled to the clamping circuit for providing a first voltage signal and a second voltage signal to trigger the clamping means to direct the electrostatic signal to ground.
In one aspect of the invention, the control means comprises a first transistor, at least one diode having a first end and a second end, and a second transistor, the first transistor being coupled to the first end of the at least one diode and the second transistor being coupled to the second end of the at least one diode.
Additionally in accordance with the present invention, there is provided an integrated circuit that includes a signal pad, a clamping circuit including a first NMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first NMOS transistor is coupled to the signal pad and the source of the first NMOS transistor is coupled to ground, and a control circuit coupled to the gate and substrate of the first NMOS transistor and the signal pad, the control circuit providing a first bias voltage signal to the gate and a second bias voltage signal to the substrate.
In one aspect of the invention, the circuit additionally includes a first diode having a first end and a second end and a second diode having a first end and a second end, wherein the first end of the first diode is coupled to the signal pad in parallel with the clamping circuit and the second end of the first diode is coupled to ground, and the first end of the second diode is coupled to a V
DD
signal and the second end of the second diode is coupled to the signal pad.
In another aspect of the invention, the control circuit includes a PMOS transistor having a source, a drain, a substrate and a gate, the source of the PMOS transistor being coupled to the signal pad, a plurality of serially coupled diodes, the drain of the PMOS transistor being coupled to a first of the plurality of serially coupled diodes, and a second NMOS transistor having a source, a drain, a gate, and a substrate, wherein the drain of the second NMOS transistor is coupled to a last of the serially coupled diodes, the source of the second NMOS transistor is coupled to ground, and the gate of the second NMOS transistor is coupled to the gate of the PMOS transistor.
In still another aspect, the substrate of the first NMOS transistor is coupled to any one of the plurality of serially coupled diodes.
In yet another aspect, the gate of the first NMOS transistor is coupled to any one of the plurality of serially coupled diodes.
Further in accordance with the present invention, there is provided an integrated circuit that includes a signal pad, a clamping circuit including a first PMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first PMOS transistor is coupled to the signal pad and the source of the first PMOS transistor is coupled to a V
DD
signal, and a control circuit is coupled to the gate and substrate of the first PMOS transistor and the signal pad, the control circuit providing a first bias voltage signal to the gate and a second bias voltage signal to the substrate.
Also in accordance with the present invention, there is provided a method for protecting an integrated circuit from electrostatic discharge that includes receiving an electrostatic si
Hung Kei-Kang
Jiang Hsin-Chin
Ker Ming-Dou
Cunningham Terry D.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Industrial Technology Research Institute
Nguyen Long
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