Dual transparent latch

Details Dual transparent latch Dual transparent latch

1992-09-29

1995-06-13

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

36518901, 36518905, G11C 800, G11C 700

Patent

active

054249961

ABSTRACT:
A dual transparent latch circuit is disclosed comprising two latches cross coupled together by two control lines to enable the latches collectively to input and output data at twice the frequency of the master clock frequency which controls the timing of each latch individually. The control lines are controlled by a clock generator such that one latch is enabled to receive and store data while the other latch is enabled to output data stored therein. At the same time, the latch receiving and storing the data is disabled from providing an output of the stored data and the latch providing the output is disabled from receiving and storing the data. The clock generator switches the states of the control lines such that they enable or disable the input of data to and output of data from the latches on each phase of the master clock signal. A dual transparent latch with triple edge timing is also disclosed. A method for generating a master signal having a master frequency and selectively enabling inputs at an input data rate greater than the master frequency to input data into memory and selectively enabling outputs at the input data rate to output data from memory.

REFERENCES:
patent: 3896417 (1975-07-01), Beecham
patent: 4628489 (1986-12-01), Ong et al.
patent: 4849935 (1989-07-01), Miyazawa
patent: 5003513 (1991-03-01), Porter et al.
patent: 5023835 (1991-06-01), Akimoto et al.
patent: 5265049 (1993-11-01), Takasugi

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