Dual-transistor structure and method of formation

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...

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257368, 257369, 257393, 257903, 257401, H01L 2701, H01L 2712, H01L 2702

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053249607

ABSTRACT:
A transistor structure (10) has a substrate (12). A first transistor is formed within the substrate (12) having a source region (38), a drain region (30), and a gate electrode formed by a first spacer (26a). A second transistor is formed within the substrate (12) by the source region (38), a drain region (28), and a gate electrode formed by a second spacer (26a). A third transistor is formed overlying the first transistor. The third transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the first spacer (26a). A fourth transistor is formed overlying the second transistor. The fourth transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the second spacer (26a). The first, second, third, and fourth transistors may be interconnected to form a portion of a compact static random access memory (SRAM) cell.

REFERENCES:
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Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI's, by Hiroshi Takato et al., was published in IEEE Trans. on Electron Devices, vol. 38, No. 3, Mar. 1991, pp. 573-577.
"Silicon-On-Insulator Gate-All-Around Device", by Colinge et al., 1990 IEEE IEDM, pp. 595-598.

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