Dual transistor output stage

Details Dual transistor output stage Dual transistor output stage

1987-10-28

1988-12-20

Wong, Peter S.

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

323274, 323350, G05F 146

Patent

active

047927453

ABSTRACT:
A circuit is provided for distributing load current among multiple power transistors in an output stage, each power transistor being adapted to conduct current over a different range of collector-emitter voltages. The circuit includes a first power transistor having a large ballast resistance for conducting current between the input and output of the circuit when the input/output voltage differential is high, and a second power transistor having a small ballast resistance for conducting current between the input and output of the circuit when the input/output voltage differential is low. Both transistors respond to a single control signal, and buffering is provided to prevent either transistor from overloading the common control point. Individual current limit protection circuitry is provided for each transistor, including a foldback network which reduces the current limit value of the current limit circuitry when the input/output voltage differential reaches a threshold value.

REFERENCES:
patent: 3704381 (1972-11-01), Nercessian
patent: 4189670 (1980-02-01), Tanahashi
patent: 4456833 (1984-06-01), Traub et al.
patent: 4644247 (1987-02-01), Burmenko

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