Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1995-11-02
2001-02-27
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S437000, C327S108000, C327S537000, C326S038000, C326S062000, C326S068000
Reexamination Certificate
active
06194945
ABSTRACT:
BACKGROUND OF THE INVENTION:
This invention relates to digital receiver circuits; and more particularly, it relates to a novel circuit structure which enables the receiver to selectively have a high threshold voltage with a large noise margin or a low threshold voltage with a large noise margin.
Conventionally, digital receiver circuits are used in various types of data processing systems where a plurality of digital logic chips are interconnected to each other. There, the receiver circuit acts as a buffer between the input terminals of a chip and the chip's internal operating circuitry. For example, one chip may be a microprocessor, and another chip may be a memory which supplies data to the microprocessor. In that case, the data is sent from the memory to the microprocessor as several bits in parallel; and each of those bits is passed through a respective receiver circuit in the microprocessor chip before being otherwise acted upon.
Each bit of data which is sent to its respective receiver circuit has a “0” voltage level and a “1” voltage level; and ideally, the receiver circuit should have a threshold voltage which is midway between the “0” and “1
4
” voltage levels. By definition, the threshold voltage of the receiver is the input voltage which causes the receiver output to be at half of the “1” voltage level. When the receiver circuit has such a threshold voltage, the difference between a “0” input voltage and the threshold voltage equals the difference between a “1” input voltage and the threshold voltage; and thus the noise margins on the input signal are as large as possible.
However, in the integrated circuit industry, new chips are continually being developed; and from time to time, a new chip is developed with a reduced “1” voltage level in comparison to the pre-existing chips. Recently, the standard “1” voltage level was reduced from 5 volts to 3.3 volts. In three to five years, it is likely that new chips will become available which have a further reduced “1” voltage level of only 2.5 volts. After that, new chips are expected to have an even further reduced “1” voltage level of only about 1.7 volts.
By reducing the “1” voltage level, the circuitry which is on an integrated circuit chip can be reduced in size; and thus, a single chip can contain more circuits per unit area. For example, a memory chip which has a “1” voltage level of 2.5 volts can contain more memory cells than a memory chip of the same size which has a “1” voltage level of 3.3 volts. However, reducing the “1” voltage level of just one particular chip presents a system problem of how to incorporate that chip into a previously designed system which has other chips that operate at a higher “1” voltage level.
Suppose, for example, that a new high density memory chip becomes available which has a reduced “1” voltage level of 2.5 volts, but no new microprocessor chip is available with the same reduced “
1
” voltage level. From a systems viewpoint it would be desirable to use the new memory chip in order to take advantage of its higher memory density. But if the new memory chip is used with a pre-existing microprocessor chip which has a “1” voltage level of 3.3 volts, then the receiver circuits in the microprocessor chip will operate with a reduced noise margin. Thus, the resulting system will be susceptible to errors which are caused by noise on the “1” or “0” voltage levels.
Accordingly, a primary object of the invention is to overcome the above problem by providing a novel structure for a receiver circuit which selectively has both a high threshold voltage with maximum noise margin and a low threshold voltage with maximum noise margin.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a dual threshold digital receiver circuit is comprised of four transistors. The first transistor and the second are interconnected in series from a voltage supply bus to a ground bus; whereas the third transistor and the fourth transistor are interconnected in series from the connection between the first and second transistors to the ground bus. An input line is connected to respective gates on the first, second, and third transistors; a control line is connected to a gate on the fourth transistor; and an output line is connected to the series connection between the first and second transistors.
In one embodiment, the receiver circuit has a high threshold of 3.3÷2 volts and maximum noise margin. This is achieved by making the first and second transistors have channel resistances, under the condition where the input line carries 3.3÷2 volts and the control line carries 0 volts, that generate an output signal as a first resistance ratio which when multiplied by the supply voltage equals 3.3÷2 volts. Further, the receiver also has a low threshold of 2.5÷2 volts and maximum noise margin. This is achieved by making all four of the transistors have respective channel resistances, under the condition where the input line carries 2.5÷2 volts and the control signal line carries 3.3 volts, that generate the output signal as a second resistance ratio which when multiplied by the supply voltage again equals 3.3÷2 volts.
REFERENCES:
patent: 4533841 (1985-08-01), Konishi
patent: 5019725 (1991-05-01), Yoshino
patent: 5216299 (1993-06-01), Wanlass
Adornato Rocco L.
Fassbender Charles J.
Le Dinh T.
Starr Mark T.
Unisys Corporation
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