Dual supply voltage pipelined ADC

Details Dual supply voltage pipelined ADC Dual supply voltage pipelined ADC

2003-06-17

2004-03-23

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C341S144000

Reexamination Certificate

active

06710735

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to pipelined analog-to-digital converters (ADCs), and in particular to a pipelined ADC having a dual supply voltage.
2. Description of Related Art
A typical digital communication transmitter encodes a data sequence to produce a waveform data sequence defining an analog signal. The transmitter then converts the waveform data sequence into the analog signal and transmits it to a receiver. An analog-to-digital converter (ADC) within the receiver periodically digitizes the analog signal to produce a waveform data sequence representing successive voltage levels of the analog signal. Digital signal processing circuits then process the waveform data sequence to recover the original data sequence. In a digital communication system operating at high data rates, the receiver must employ a high resolution ADC that can sample the analog signal at a high frequency. For example, a very high speed broadband access digital subscriber loop (VDSL) offering downstream data rates up to 52 Mbps needs an ADC providing 12 effective bits of resolution at a sample rate of 35 MHZ.
A pipelined ADC employing a sequence of low-resolution ADC stages to digitize an analog signal with high resolution is well suited for high-speed, high-resolution applications. The following U.S. patents incorporated herein by reference describe various pipelined ADC architectures:
U.S. Pat. No. 6,169,502, issued Jan. 2, 2001 to Johnson et al.,
U.S. Pat. No. 6,366,230, issued Apr. 2, 2002 to Zhang et al., and
U.S. Pat. No. 6,456,223, issued Sep. 24, 2002 to Yu et al.
FIG. 1
illustrates a typical prior art pipelined ADC
10
including a set of N ADC stages
12
(
1
)-
12
(N) and a set of N−1 shift registers
14
(
1
)-(N−1). A differential analog signal A(
1
) to be digitized is applied as input to the first stage
12
(
1
). In response to each n
th
leading (or trailing) edge of a clock signal (CLOCK), each i
th
stage
12
(i) samples the voltage of its analog input signal A(i) and produces a B-bit data word x
i
(n)
approximating the magnitude of the sampled input signal voltage with B-bit resolution. Each i
th
stage
12
(i) other than the last stage
12
(N) also supplies an output differential analog residue signal A(i+1) as an input signal to the next stage
12
(i+1) wherein
A
(
i
+1)=2
B
[A
(
i
)−(VMAX/2
B
)(
x
i
(n)
−2
B−1
+½)]
where VMAX is the peak-to-pak full range voltage of the stage's differential input signal A(i). The output residue signal A(i+1) of each i
th
stage
12
(i) is thus proportional to the error difference between the sampled voltage of its input signal A(i) and the voltage level represented by the stage output data x
i
(n)
.
For example a pipelined DAC for which B=2, VMAX=5 volts, and N=3 stages could digitize an input signal A(
1
) ranging from −2.5V to 2.5V with BxN=6-bit resolution. With B=2, each i
th
data word x
i
(n)
can have any of four 2-bit values representing −1.875, −0.625 or 1.875 volts. Thus when A(
1
) is, for example, 0.4 volts when sampled on an n
th
CLOCK signal pulse, the first stage output data is
x
1
(n)
=10(binary)
representing a magnitude of 0.625 volts which approximates the actual 0.4 volt magnitude of the A(
1
) signal. The stage
1
output residue signal A(
2
) will be
A
(
2
)=2
2
[0.4−({fraction (5/4)})(2−1.5)]=2
2
[0.4−0.625]=−0.9 volts
On the (n+1)
th
CLOCK signal edge, second stage
12
(
2
) will digitize the −0.9 volt A(
2
) signal to produce output data
x
2
(n−1)
=01(binary)
corresponding to a magnitude of −0.625 volts approximating the −0.9 volt A(
2
) signal. The second state output analog signal A(
3
) has magnitude
A
(
3
)=2
2
[−0.9−({fraction (5/4)})(1−1.5)]=2
2
[−0.9+0.625]=−1.1 volts.
On the (n+2)
th
CLOCK signal edge, the final pipeline stage
12
(
3
) will digitize the 1.4 volt A(
3
) signal to produce output data
x
3
(n+2)
=01(binary)
corresponding to a measured value of −0.625 volts.
Successive stages
12
(
1
)-
12
(N) produce their output data x
1
(n)
-x
N
(n)
with progressively larger delays. Therefore shift registers
14
(
1
)-
14
(N−1) delay successive stage output data by progressively decreasing delays so that they concurrently produce output data x
1
(n−N+1)
-x
N
(n)
that can be combined to form a single NxB-bit OUTPUT word representing the magnitude of the A(
1
) input signal when sampled by stage
12
(
1
) N CLOCK signal cycles earlier. In the example case the ADC's digital OUTPUT word value will be
OUTPUT={
X
3
(n)
, X
2
(n−N+2)
, X
1
(n−N+1)
}=100101(binary) =37(decimal)
The OUTPUT word value, which can range from 0 to 2
6
−1, represents the sampled magnitude of input signal A(
1
) with 6-bit resolution. In this example the OUTPUT word represents an input signal voltage
A
(
1
)=(VMAX/2
6
)×(OUTPUT−2
5
+½) =({fraction (5/64)})5.5 =0.429 volts
which is as close to the actual 0.4 volts of ADC input signal A(
1
) as can be represented given a −2.5 to 2.5 volt range and 6-bit resolution.
FIG. 2
illustrates an example architecture for stage
12
(
1
) of the pipelined ADC of FIG.
1
. Stages
12
(
2
)-
12
(N−1) are similar. An amplifier
24
amplifies the differential A(
1
) signal to produce sample voltage A′ (
1
). A sample and hold (S/H) circuit
16
samples and holds A′ (
1
) on each leading or trailing edge of the CLOCK signal and the sample voltage A′ (
1
) stored in S&H circuit
16
is supplied to a B-bit ADC
18
. ADC digitizes A′ (
1
) to produce B-bit output data x
1
(n)
. A B-bit digital-to-analog converter (ADC)
20
converts x
1
(n)
into an offset voltage
V
OFF
=(VMAX/2
B
)(
x
1
(n)
−2
B−1
+½).
An analog summing amplifier
22
offsets A′ (
1
) by V
OFF
to produce the differential stage output residue signal A(
2
).
FIG. 3
depicts an example of final stage
12
(N) of
FIG. 1
that is similar to stage
12
(
1
) of
FIG. 2
except that it omits DAC and summing amplifier
22
.
Error Sources
Various factors can compromise the accuracy of the pipelined ADC
10
of
FIGS. 1-3
including, for example:
1. thermal noise,
2. comparator offset error within the ADC
18
of any stage,
3. error in the gain of amplifier
24
of any stage,
4. nonlinearity of ADC
18
,
5. nonlinearity of DAC
20
,
6. nonlinearity of amplifier
24
, and
7. incomplete settling of output residue signal A(
2
).
Among the above sources of error, only thermal noise is random and varies from sample-to-sample. The other sources of error, mainly mismatches in circuit elements such as transistor dimensions, resistor and capacitor values, are “systematic” in that they are consistent from sample-to-sample. Many correction and calibration techniques are available to significantly improve the accuracy of ADCs by compensating for systematic errors. For example it is possible to substantially reduce systematic errors by adjusting the gain and offset of the amplifier
24
in one or more stages. Thus the accuracy of modern pipelined ADCs is typically limited by thermal noise rather than by systematic errors.
In response to each leading or trailing edge of the CLOCK signal, S&H circuit
16
briefly connects the sample voltage A′ (
1
) signal to an internal capacitor so that amplifier
24
producing the A′ (
1
) signal can charge the capacitor to the current A′ (
1
) signal voltage. The capacitor voltage remains at the sampled signal A′ (
1
) voltage for the remainder of the CLOCK cycle to allow the A(
2
) and X
1
(n)
stage outputs time to settle to new levels.
The sampling capacitor actually remains only approximately at the samp

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